| Asset ID: |
1-71-2085572.1 |
| Update Date: | 2017-12-21 |
| Keywords: | |
Solution Type
Technical Instruction Sure
Solution
2085572.1
:
SPARC M7 Series Servers : SP or SPP FPGA firmware update
| Related Categories |
- PLA-Support>Sun Systems>SPARC>Enterprise>SN-SPARC: M7
|
In this Document
Oracle Confidential PARTNER - Available to partners (SUN).
Reason: FRU
Applies to:
SPARC M7-16 - Version All Versions and later
SPARC M7-8 - Version All Versions and later
Information in this document applies to any platform.
Goal
The goal of this document is to describe how to upgrade the SP or SPP FPGA Firmware on SPARC M7 series server.
The platform should be running SysFW 9.5.2.g or higher.
Note that several components of the SPARC M7 Series Servers are using FPGA. Those components must be running the latest version.
The following table provides the list of components and the respective latest versions available.
| Platform Type |
Component |
FPGA Version |
| M7-16, M7-8 with one or 2 Pdoms |
CMIOU |
X.3.8.3 |
| M7-16, M7-8 with one or 2 Pdoms |
SP |
15.1.3.4 |
| M7-16 |
SPP |
15.1.3.4 |
| M7-16 |
SWU |
Y.2.0.5 |
If the platform is having several components running with downrev FPGA then all of the components should be updated.
This document also contains the procedure to check the FPGA versions and how to update. See section 4. below.
When replacing an SP or SPP on M7-8 or M7-16 servers, the procedure described below must be applied to check and update the FPGA version running on the newly installed SP/SPP.
Updating the FPGA requires to power cycle the component. A complete platform power cycle is not required.
This document provides the methods to perform this operation.
Solution
1. How to check the FPGA versions
It's possible to check the FPGA versions from Restricted Shell on the Active SP.
Example from an M7-16 server :
[(restricted_shell) m7-16-sp:~]# hw version | grep "M7_FPGA"
19. /SYS/CMIOU0/FPGA (M7_FPGA) Version: 7.3.7.5
65. /SYS/CMIOU1/FPGA (M7_FPGA) Version: 7.3.7.5
111. /SYS/CMIOU4/FPGA (M7_FPGA) Version: 7.3.7.5
157. /SYS/CMIOU5/FPGA (M7_FPGA) Version: 7.3.7.5
203. /SYS/CMIOU8/FPGA (M7_FPGA) Version: 7.3.7.5
249. /SYS/CMIOU9/FPGA (M7_FPGA) Version: 7.3.7.5
295. /SYS/CMIOU12/FPGA (M7_FPGA) Version: 7.3.7.5
341. /SYS/CMIOU13/FPGA (M7_FPGA) Version: 7.3.7.5
401. /SYS/SP0/FPGA (M7_FPGA) Version: 15.1.2.11
412. /SYS/SP1/FPGA (M7_FPGA) Version: 15.1.2.11
423. /SYS/SPP0/FPGA (M7_FPGA) Version: 15.1.2.11
435. /SYS/SPP1/FPGA (M7_FPGA) Version: 15.1.2.11
447. /SYS/SPP2/FPGA (M7_FPGA) Version: 15.1.2.11
459. /SYS/SPP3/FPGA (M7_FPGA) Version: 15.1.2.11
477. /SYS/SWU0/FPGA (M7_FPGA) Version: 6.2.0.2
502. /SYS/SWU1/FPGA (M7_FPGA) Version: 6.2.0.2
527. /SYS/SWU2/FPGA (M7_FPGA) Version: 6.2.0.2
552. /SYS/SWU3/FPGA (M7_FPGA) Version: 6.2.0.2
577. /SYS/SWU4/FPGA (M7_FPGA) Version: 6.2.0.2
602. /SYS/SWU5/FPGA (M7_FPGA) Version: 6.2.0.2
Note : You can safely ignore any "idtxx_version call failed version=" messages.
Note that this information is also collected by ILOM Snapshot; in the ilom/@usr@local@bin@hw_version_-local.out file.
Example from an M7-8 server
-bash-4.1$ grep "M7_FPGA" ilom/@usr@local@bin@hw_version_-local.out
19. /SYS/CMIOU0/FPGA (M7_FPGA) Version: 7.3.7.5
65. /SYS/CMIOU1/FPGA (M7_FPGA) Version: 7.3.7.5
111. /SYS/CMIOU2/FPGA (M7_FPGA) Version: 7.3.7.5
157. /SYS/CMIOU3/FPGA (M7_FPGA) Version: 7.3.7.5
184. /SYS/SP0/FPGA (M7_FPGA) Version: 15.1.2.11
Example from an M7-16 server
-bash-4.1$ grep "M7_FPGA" ilom/*hw*
9. /SYS/SP0/FPGA (M7_FPGA) Version: 15.1.2.11
26. /SYS/SWU0/FPGA (M7_FPGA) Version: 6.2.0.2
51. /SYS/SWU1/FPGA (M7_FPGA) Version: 6.2.0.2
76. /SYS/SWU2/FPGA (M7_FPGA) Version: 6.2.0.2
101. /SYS/SWU3/FPGA (M7_FPGA) Version: 6.2.0.2
126. /SYS/SWU4/FPGA (M7_FPGA) Version: 6.2.0.2
151. /SYS/SWU5/FPGA (M7_FPGA) Version: 6.2.0.2
-bash-4.1$ grep "/FPGA" spp_snapshot/*/ilom/*hw*
spp_snapshot/SPP0@SPM0/ilom/@usr@local@bin@hw_version_-local.out:19. /SYS/CMIOU0/FPGA (M7_FPGA) Version: 7.3.7.5
spp_snapshot/SPP0@SPM0/ilom/@usr@local@bin@hw_version_-local.out:65. /SYS/CMIOU1/FPGA (M7_FPGA) Version: 7.3.7.5
spp_snapshot/SPP0@SPM0/ilom/@usr@local@bin@hw_version_-local.out:105. /SYS/SPP0/FPGA (M7_FPGA) Version: 15.1.2.11
spp_snapshot/SPP1@SPM0/ilom/@usr@local@bin@hw_version_-local.out: 1. /SYS/SPP1/FPGA (M7_FPGA) Version: 15.1.2.11
spp_snapshot/SPP1@SPM1/ilom/@usr@local@bin@hw_version_-local.out:19. /SYS/CMIOU4/FPGA (M7_FPGA) Version: 7.3.7.5
spp_snapshot/SPP1@SPM1/ilom/@usr@local@bin@hw_version_-local.out:65. /SYS/CMIOU5/FPGA (M7_FPGA) Version: 7.3.7.5
spp_snapshot/SPP2@SPM0/ilom/@usr@local@bin@hw_version_-local.out:19. /SYS/CMIOU8/FPGA (M7_FPGA) Version: 7.3.7.5
spp_snapshot/SPP2@SPM0/ilom/@usr@local@bin@hw_version_-local.out:65. /SYS/CMIOU9/FPGA (M7_FPGA) Version: 7.3.7.5
spp_snapshot/SPP2@SPM0/ilom/@usr@local@bin@hw_version_-local.out:105. /SYS/SPP2/FPGA (M7_FPGA) Version: 15.1.2.11
spp_snapshot/SPP3@SPM0/ilom/@usr@local@bin@hw_version_-local.out: 1. /SYS/SPP3/FPGA (M7_FPGA) Version: 15.1.2.11
spp_snapshot/SPP3@SPM1/ilom/@usr@local@bin@hw_version_-local.out:19. /SYS/CMIOU12/FPGA (M7_FPGA) Version: 7.3.7.5
spp_snapshot/SPP3@SPM1/ilom/@usr@local@bin@hw_version_-local.out:65. /SYS/CMIOU13/FPGA (M7_FPGA) Version: 7.3.7.5
If several components are reporting downrev FPGA version compared to the following table then refer to the procedure available in point 4. below.
| Platform Type |
Component |
FPGA Version |
| M7-16, M7-8 with one or 2 Pdoms |
CMIOU |
X.3.8.3 |
| M7-16, M7-8 with one or 2 Pdoms |
SP |
15.1.3.4 |
| M7-16 |
SPP |
15.1.3.4 |
| M7-16 |
SWU |
Y.2.0.5 |
In the context of an SP or SPP replacement, please refer to the procedure described in point 3. below.
2. Obtain the firmware image from MOS
Log to My Oracle Support, from the Patches and Updates tab, "Patch Search" select "Product or Family (Advanced)".
Select the Product as SPARC M7-8 or M7-16 and from the Release list, select ...
Click Search and download the appropriate image.
| HWP |
Patch |
FW revision |
README File |
| 1.0.6.a |
26970558 |
X.3.8.3 / 15.1.3.4 / Y.2.0.5 |
README |
Always refer to the associated README file for any specific instruction.
The downloaded zip file contains the .pkg file : Hardware_Programmables-1.0.6.a-SPARC_M7-Systems.pkg
This single .pkg file contains the FPGA images for all of the components (CMIOU, SWU and SP/SPP).
Place the firmware image on a server supporting one of the following protocols:
TFTP, FTP, SFTP, SCP, HTTP, or HTTPS.
3. Update SP/SPP FPGA upon SP/SPP replacement
When replacing an SP/SPP in an M7-8 or M7-16 server, the new SP/SPP is more likely running a downrev FPGA.
Replacing an SP/SPP, it's not required to stop any physical domain. The SP/SPP being replaced is not the Active SP and not a DCU or PDOM SPM, so there is no impact on any of the running hosts.
3.1 SP/SPP replacement
The SP/SPP replacement procedure is described in :
Please follow the procedure to physically replace the SP/SPP.
After inserting the new SP/SPP, when the SP/SPP is restarting, you will see the following message in the event logs :
-> show /SP/logs/event/list/
Event
ID Date/Time Class Type Severity
----- ------------------------ -------- -------- --------
209 Mon Dec 14 19:22:08 2015 Chassis Log major
/SYS/SP1/FPGA update required.
208 Mon Dec 14 19:14:04 2015 Chassis Action major
Hot insertion of /SYS/SP1
207 Mon Dec 14 19:14:02 2015 Chassis Action major
Hot insertion of /SYS/SP1/SPM0
The message basically confirms that an FPGA upgrade is required. You should process with the next step : FPGA update.
3.2 FPGA update
To update the SP/SPP FPGA, please follow the following procedure.
After the new SP/SPP has been inserted, from the Active SP, apply the downloaded FPGA image by running
The load command supports the following protocols : TFTP, FTP, SFTP, SCP, HTTP, or HTTPS.
The SP/SPP FPGA update will take up to 15 minutes to complete. But the whole process will take more time to complete.
Do NOT power cycle any components until this script is reporting success.
Example from an M7-8 with the host up :
-> load -source sftp://use@hostname/tmp/Hardware_Programmables-1.0.6.a-SPARC_M7-Systems.pkg
Enter remote user password: *********
NOTE: An upgrade takes several minutes to complete. ILOM
will enter a special mode to load new firmware. No
other tasks can be performed in ILOM until the
firmware upgrade is complete and ILOM is reset.
NOTE: HOST0 is powered on; HOST0 firmware will be updated
automatically when HOST0 is restarted.
Are you sure you want to load the specified file (y/n)? y
2015-12-14 19:31:04 Install firmware package...
Version: 100.1.0.6
....Finish update of: FPGA Update v1.0.6 for M7.
************************************************************
WARNING: the script can take a very long time to finish.
(Up to 15 minutes per SP, SPP, CMIOU, and SWU board)
DO NOT INTERRUPT the script, it may result in a dead board.
************************************************************
2015-12-14 19:44:18 Found /SYS/SP0/SPM0, Active
2015-12-14 19:44:20 Found /SYS/SP1/SPM0, Standby
2015-12-14 19:44:28 Copying script to the SPMs...
2015-12-14 19:44:30 Copying FPGA image to the SPMs...
2015-12-14 19:45:44 Running FPGA update on /SYS/SP0/SPM0
2015-12-14 19:45:44 Running FPGA update on /SYS/SP1/SPM0
....................................................................................................................................................................
2015-12-14 20:03:57 /SYS/SP0/SPM0 : CMIOU0 FPGA verify success
2015-12-14 20:03:57 /SYS/SP0/SPM0 : CMIOU1 FPGA verify success
2015-12-14 20:03:57 /SYS/SP0/SPM0 : CMIOU2 FPGA verify success
2015-12-14 20:03:58 /SYS/SP0/SPM0 : CMIOU3 FPGA verify success
2015-12-14 20:03:58 /SYS/SP0/SPM0 : CMIOU4 FPGA verify success
2015-12-14 20:03:58 /SYS/SP0/SPM0 : CMIOU5 FPGA verify success
2015-12-14 20:03:58 /SYS/SP0/SPM0 : SP FPGA verify success
2015-12-14 20:03:58 /SYS/SP1/SPM0 : SP FPGA update success
2015-12-14 20:03:58 FPGAs are at the latest revision.
2015-12-14 20:03:58 All done.
Finished updates
Firmware update is complete.
2015-12-14 20:04:10 Completed install
-> show /SP/logs/event/list/
Event
ID Date/Time Class Type Severity
----- ------------------------ -------- -------- --------
220 Mon Dec 14 20:03:58 2015 Firmware Update minor
Performing FPGA update on /SYS/SP1/SPM0 : SP FPGA success
219 Mon Dec 14 20:03:58 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : SP FPGA success
218 Mon Dec 14 20:03:58 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU5 FPGA success
217 Mon Dec 14 20:03:58 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU4 FPGA success
216 Mon Dec 14 20:03:58 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU3 FPGA success
215 Mon Dec 14 20:03:58 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU2 FPGA success
214 Mon Dec 14 20:03:57 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU1 FPGA success
213 Mon Dec 14 20:03:57 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU0 FPGA success
212 Mon Dec 14 20:03:57 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU6 FPGA success
Note : In the above examples, SP0 FPGA was up to date and no update was required.
Note : In the above, the 2 * "NOTE:" and message about ILOM and host restart are irrelevant as no SP or host reset is required
Example from an M7-16 with the host up :
-> load -source scp://user@hostname/tmp/Hardware_Programmables-1.0.6.a-SPARC_M7-Systems.pkg
Enter remote user password: *********
NOTE: An upgrade takes several minutes to complete. ILOM
will enter a special mode to load new firmware. No
other tasks can be performed in ILOM until the
firmware upgrade is complete and ILOM is reset.
NOTE: HOST0 is powered on; HOST0 firmware will be updated
automatically when HOST0 is restarted.
NOTE: HOST3 is powered on; HOST3 firmware will be updated
automatically when HOST3 is restarted.
Are you sure you want to load the specified file (y/n)? y
2015-12-15 17:16:36 Install firmware package...
Version: 100.1.0.6
Finish update of: FPGA Update v1.0.6 for M7.
************************************************************
WARNING: the script can take a very long time to finish.
(Up to 15 minutes per SP, SPP, CMIOU, and SWU board)
DO NOT INTERRUPT the script, it may result in a dead board.
************************************************************
2015-12-15 17:18:38 Found /SYS/SP0/SPM0, Active
2015-12-15 17:18:41 Found /SYS/SP1/SPM0, Standby
2015-12-15 17:18:43 Found /SYS/SPP0/SPM0, Proxy Golden
2015-12-15 17:18:45 Found /SYS/SPP0/SPM1, Proxy Inactive
2015-12-15 17:18:47 Found /SYS/SPP1/SPM0, Proxy Inactive
2015-12-15 17:18:49 Found /SYS/SPP1/SPM1, Proxy Golden
2015-12-15 17:18:52 Found /SYS/SPP2/SPM0, Proxy Golden
2015-12-15 17:18:55 Found /SYS/SPP2/SPM1, Proxy Golden
2015-12-15 17:18:57 Found /SYS/SPP3/SPM0, Proxy Inactive
2015-12-15 17:18:59 Found /SYS/SPP3/SPM1, Proxy Inactive
2015-12-15 17:19:48 Copying script to the SPMs...
2015-12-15 17:19:54 Copying FPGA image to the SPMs...
2015-12-15 17:22:59 Running FPGA update on /SYS/SPP2/SPM1
2015-12-15 17:22:59 Running FPGA update on /SYS/SPP2/SPM0
2015-12-15 17:22:59 Running FPGA update on /SYS/SPP3/SPM0
2015-12-15 17:22:59 Running FPGA update on /SYS/SP1/SPM0
2015-12-15 17:22:59 Running FPGA update on /SYS/SPP0/SPM0
2015-12-15 17:22:59 Running FPGA update on /SYS/SPP1/SPM0
2015-12-15 17:23:00 Running FPGA update on /SYS/SPP1/SPM1
2015-12-15 17:23:00 Running FPGA update on /SYS/SP0/SPM0
...........................................................................................................................................................
2015-12-15 17:41:14 /SYS/SP0/SPM0 : SWU0 FPGA verify success
2015-12-15 17:41:14 /SYS/SP0/SPM0 : SP FPGA verify success
2015-12-15 17:41:14 /SYS/SP0/SPM0 : SWU1 FPGA verify success
2015-12-15 17:41:14 /SYS/SP0/SPM0 : SWU2 FPGA verify success
2015-12-15 17:41:14 /SYS/SP0/SPM0 : SWU3 FPGA verify success
2015-12-15 17:41:15 /SYS/SP0/SPM0 : SWU4 FPGA verify success
2015-12-15 17:41:15 /SYS/SP0/SPM0 : SWU5 FPGA verify success
2015-12-15 17:41:15 /SYS/SP1/SPM0 : SP FPGA verify success
2015-12-15 17:41:15 /SYS/SPP0/SPM0 : CMIOU0 FPGA verify success
2015-12-15 17:41:15 /SYS/SPP0/SPM0 : CMIOU1 FPGA verify success
2015-12-15 17:41:15 /SYS/SPP0/SPM0 : SP FPGA verify success
2015-12-15 17:41:16 /SYS/SPP1/SPM0 : SP FPGA verify success
2015-12-15 17:41:16 /SYS/SPP1/SPM1 : CMIOU4 FPGA verify success
2015-12-15 17:41:16 /SYS/SPP1/SPM1 : CMIOU5 FPGA verify success
2015-12-15 17:41:16 /SYS/SPP2/SPM0 : CMIOU8 FPGA verify success
2015-12-15 17:41:16 /SYS/SPP2/SPM0 : CMIOU9 FPGA verify success
2015-12-15 17:41:16 /SYS/SPP2/SPM0 : SP FPGA verify success
2015-12-15 17:41:17 /SYS/SPP2/SPM1 : CMIOU12 FPGA verify success
2015-12-15 17:41:17 /SYS/SPP2/SPM1 : CMIOU13 FPGA verify success
2015-12-15 17:41:17 /SYS/SPP3/SPM0 : SP FPGA update success
2015-12-15 17:41:17 FPGAs are at the latest revision.
2015-12-15 17:41:17 All done.
Finished updates
Firmware update is complete.
2015-12-15 17:41:25 Completed install
-> show /SP/logs/event/list/
Event
ID Date/Time Class Type Severity
----- ------------------------ -------- -------- --------
1375 Tue Dec 15 17:41:17 2015 Firmware Update minor
Performing FPGA update on /SYS/SPP3/SPM0 : SP FPGA success
Note : If the command reports a failure, re-run the command. If the command fails again, contact Service and the owner of the SR.
At this point, the FPGA image has not yet been applied. An SP/SPP power cycle is required. This can be done by unseating and reseating the SP/SPP.
As described below :
This procedure is also documented in the SPARC M7 Series Servers Service Manual.
Note : In order to power cycle the component, after replacing the SP/SPP, instead of unseating/reseating the SP/SPP, it's also possible to power cycle the platform (by switching off/on the respective breakers on the rack). PDU breakers switch on/off sequences are described in the Service Manual:
Of course, this method will require all of the running hosts to be stopped and this will extend the maintenance window as the SP and/or SPP will reset.
Check from Restricted Shell that the SP/SPP is now running the latest version
[(restricted_shell) m7-16-sp:~]# hw version | grep SP | grep "M7_FPGA"
And confirm from the above output that all of the SP/SPPs are running the same FPGA version.
[(restricted_shell) m7-8-sp0:~]# hw version | grep "M7_FPGA"
...
335. /SYS/SP0/FPGA (M7_FPGA) Version: 15.1.3.4
347. /SYS/SP1/FPGA (M7_FPGA) Version: 15.1.3.4
[(restricted_shell) m7-16-sp0:~]# hw version | grep "M7_FPGA"
...
401. /SYS/SP0/FPGA (M7_FPGA) Version: 15.1.3.4
412. /SYS/SP1/FPGA (M7_FPGA) Version: 15.1.3.4
423. /SYS/SPP0/FPGA (M7_FPGA) Version: 15.1.3.4
435. /SYS/SPP1/FPGA (M7_FPGA) Version: 15.1.3.4
447. /SYS/SPP2/FPGA (M7_FPGA) Version: 15.1.3.4
459. /SYS/SPP3/FPGA (M7_FPGA) Version: 15.1.2.11
3.3 No update required
When running the command, if no update is required, the command will just return as following :
-> load -source sftp://user@hostname/tmp/Hardware_Programmables-1.0.6.a-SPARC_M7-Systems.pkg
Enter remote user password: *********
NOTE: An upgrade takes several minutes to complete. ILOM
will enter a special mode to load new firmware. No
other tasks can be performed in ILOM until the
firmware upgrade is complete and ILOM is reset.
NOTE: HOST0 is powered on; HOST0 firmware will be updated
automatically when HOST0 is restarted.
Are you sure you want to load the specified file (y/n)? y
2015-12-14 22:11:30 Install firmware package...
Version: 100.1.0.6
..Finish update of: FPGA Update v1.0.6 for M7.
************************************************************
WARNING: the script can take a very long time to finish.
(Up to 15 minutes per SP, SPP, CMIOU, and SWU board)
DO NOT INTERRUPT the script, it may result in a dead board.
************************************************************
2015-12-14 22:24:42 Found /SYS/SP0/SPM0, Active
2015-12-14 22:24:44 Found /SYS/SP1/SPM0, Standby
2015-12-14 22:24:50 Copying script to the SPMs...
2015-12-14 22:24:52 Copying FPGA image to the SPMs...
2015-12-14 22:26:08 Running FPGA update on /SYS/SP0/SPM0
2015-12-14 22:26:08 Running FPGA update on /SYS/SP1/SPM0
......................................................................................................................................................
2015-12-14 22:38:40 /SYS/SP0/SPM0 : CMIOU0 FPGA verify success
2015-12-14 22:38:40 /SYS/SP0/SPM0 : CMIOU1 FPGA verify success
2015-12-14 22:38:40 /SYS/SP0/SPM0 : CMIOU2 FPGA verify success
2015-12-14 22:38:40 /SYS/SP0/SPM0 : CMIOU3 FPGA verify success
2015-12-14 22:38:40 /SYS/SP0/SPM0 : CMIOU4 FPGA verify success
2015-12-14 22:38:40 /SYS/SP0/SPM0 : CMIOU5 FPGA verify success
2015-12-14 22:38:41 /SYS/SP0/SPM0 : CMIOU6 FPGA verify success
2015-12-14 22:38:41 /SYS/SP0/SPM0 : SP FPGA verify success
2015-12-14 22:38:41 /SYS/SP1/SPM0 : SP FPGA verify success
2015-12-14 22:38:41 FPGAs are at the latest revision.
2015-12-14 22:38:41 All done.
Finished updates
Firmware update is complete.
2015-12-14 22:38:54 Completed install
-> show /SP/logs/event/list/
Event
ID Date/Time Class Type Severity
----- ------------------------ -------- -------- --------
248 Mon Dec 14 22:38:41 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP1/SPM0 : SP FPGA success
247 Mon Dec 14 22:38:41 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : SP FPGA success
246 Mon Dec 14 22:38:41 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU6 FPGA success
245 Mon Dec 14 22:38:41 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU5 FPGA success
244 Mon Dec 14 22:38:40 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU4 FPGA success
243 Mon Dec 14 22:38:40 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU3 FPGA success
242 Mon Dec 14 22:38:40 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU2 FPGA success
241 Mon Dec 14 22:38:40 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU1 FPGA success
240 Mon Dec 14 22:38:40 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU0 FPGA success
4. Update FPGA for more than one component
If more than one component require FPGA update, the preferred method is probably to :
- Stop all of the running hosts
- From the Active SP, apply the downloaded FPGA image by running
The load command supports the following protocols : TFTP, FTP, SFTP, SCP, HTTP, or HTTPS.
The update will take up to 15 minutes per SP, SPP, CMIOU, and SWU board. But the whole process will take more time to complete.
Do NOT power cycle any components until this script is reporting success.
Example :
-> load -source sftp://user@hostname//snaps/SPARC/M7/p22345376_106/Firmware/Hardware_Programmables/Hardware_Programmables-1.0.6.a-SPARC_M7-Systems.pkg
Enter remote user password: *********
NOTE: An upgrade takes several minutes to complete. ILOM
will enter a special mode to load new firmware. No
other tasks can be performed in ILOM until the
firmware upgrade is complete and ILOM is reset.
NOTE: HOST0 is powered on; HOST0 firmware will be updated
automatically when HOST0 is restarted.
Are you sure you want to load the specified file (y/n)? y
2015-12-14 17:20:29 Install firmware package...
Version: 100.1.0.6
..Finish update of: FPGA Update v1.0.6 for M7.
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WARNING: the script can take a very long time to finish.
(Up to 15 minutes per SP, SPP, CMIOU, and SWU board)
DO NOT INTERRUPT the script, it may result in a dead board.
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2015-12-14 17:40:07 Found /SYS/SP0/SPM0, Stand-alone
2015-12-14 17:40:11 Copying script to the SPMs...
2015-12-14 17:40:12 Copying FPGA image to the SPMs...
2015-12-14 17:41:11 Running FPGA update on /SYS/SP0/SPM0
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2015-12-14 18:34:48 /SYS/SP0/SPM0 : CMIOU0 FPGA update success
2015-12-14 18:34:48 /SYS/SP0/SPM0 : CMIOU1 FPGA update success
2015-12-14 18:34:48 /SYS/SP0/SPM0 : CMIOU2 FPGA update success
2015-12-14 18:34:48 /SYS/SP0/SPM0 : CMIOU3 FPGA update success
2015-12-14 18:34:49 /SYS/SP0/SPM0 : CMIOU4 FPGA update success
2015-12-14 18:34:49 /SYS/SP0/SPM0 : CMIOU5 FPGA update success
2015-12-14 18:34:49 /SYS/SP0/SPM0 : SP FPGA update success
2015-12-14 18:34:49 FPGAs are at the latest revision.
2015-12-14 18:34:49 All done.
Finished updates
Firmware update is complete.
2015-12-14 18:35:04 Completed install
Note : In the above, the 2 * "NOTE:" and message about ILOM and host restart are irrelevant as no SP or host reset is required
Note : If the command reports a failure, re-run the command. If the command fails again, contact Service and the owner of the SR.
-> show /SP/logs/event/list
Event
ID Date/Time Class Type Severity
----- ------------------------ -------- -------- --------
174 Mon Dec 14 18:34:49 2015 Firmware Update minor
Performing FPGA update on /SYS/SP0/SPM0 : SP FPGA success
173 Mon Dec 14 18:34:49 2015 Firmware Update minor
Performing FPGA update on /SYS/SP0/SPM0 : CMIOU5 FPGA success
172 Mon Dec 14 18:34:49 2015 Firmware Update minor
Performing FPGA update on /SYS/SP0/SPM0 : CMIOU4 FPGA success
171 Mon Dec 14 18:34:49 2015 Firmware Update minor
Performing FPGA update on /SYS/SP0/SPM0 : CMIOU3 FPGA success
170 Mon Dec 14 18:34:48 2015 Firmware Update minor
Performing FPGA update on /SYS/SP0/SPM0 : CMIOU2 FPGA success
169 Mon Dec 14 18:34:48 2015 Firmware Update minor
Performing FPGA update on /SYS/SP0/SPM0 : CMIOU1 FPGA success
168 Mon Dec 14 18:34:48 2015 Firmware Update minor
Performing FPGA update on /SYS/SP0/SPM0 : CMIOU0 FPGA success
At this point, the FPGA image has not yet been applied. A power cycle is required.
- Power cycle the platform (by switching off/on the respective breakers on the rack). PDU breakers switch on/off sequences are described in the Service Manual:
-
When all of the SP/SPP are back online, check from Restricted Shell on the Active SP that the components is now running the latest version
[(restricted_shell) m7-16-sp:~]# hw version | grep "M7_FPGA"
And confirm from the above output that all of the components are running the latest FPGA versions.
- The hosts can now be restarted
-> start /System
Are you sure you want to start all of the configured hosts on the system (y/n)? y
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