SPARC M7 Series Servers : CMIOU FPGA firmware update

Asset ID:	1-71-2085049.1
Update Date:	2017-12-21
Keywords:

Solution Type Technical Instruction Sure

Solution 2085049.1 : SPARC M7 Series Servers : CMIOU FPGA firmware update

Applies to:

SPARC M7-16 - Version All Versions and later
SPARC M7-8 - Version All Versions and later
Information in this document applies to any platform.

Goal

The goal of this document is to describe how to upgrade the CMIOU FPGA Firmware on SPARC M7 series server.

The platform should be running SysFW 9.5.2.g or higher.

Note that several components of the SPARC M7 Series Servers are using FPGA. Those components must be running the latest version.

The following table provides the list of components and the respective latest versions available.

Platform Type	Component	FPGA Version
M7-16, M7-8 with one or 2 Pdoms	CMIOU	X.3.8.3
M7-16, M7-8 with one or 2 Pdoms	SP	15.1.3.4
M7-16	SPP	15.1.3.4
M7-16	SWU	Y.2.0.5

Where X and Y can be ignored.

If the platform is having several components running with downrev FPGA then all of the components should be updated. See Section 4. below.

This document also contains the procedure to check the FPGA versions and how to update.

When replacing a CMIOU on M7-8 or M7-16 servers, the procedure described below must be applied to check and update the FPGA version running on the newly installed CMIOU.

Updating the FPGA requires to power cycle the component. A complete platform power cycle is NOT required. This can be done by reseating the CMIOU.

This document provides the methods to perform this operation.

Solution

1. How to check the FPGA versions

It's possible to check the FPGA versions from Restricted Shell on the Active SP.

Example from an M7-16 server :

-> set SESSION mode=restricted

WARNING: The "Restricted Shell" account is provided solely
to allow Services to perform diagnostic tasks.

[(restricted_shell) m7-16-sp:~]# hw version | grep "M7_FPGA"
19. /SYS/CMIOU0/FPGA (M7_FPGA)               Version: 7.3.7.5
65. /SYS/CMIOU1/FPGA (M7_FPGA)               Version: 7.3.7.5
111. /SYS/CMIOU4/FPGA (M7_FPGA)              Version: 7.3.7.5
157. /SYS/CMIOU5/FPGA (M7_FPGA)              Version: 7.3.7.5
203. /SYS/CMIOU8/FPGA (M7_FPGA)              Version: 7.3.7.5
249. /SYS/CMIOU9/FPGA (M7_FPGA)              Version: 7.3.7.5
295. /SYS/CMIOU12/FPGA (M7_FPGA)             Version: 7.3.7.5
341. /SYS/CMIOU13/FPGA (M7_FPGA)             Version: 7.3.7.5
401. /SYS/SP0/FPGA (M7_FPGA)                 Version: 15.1.2.11
412. /SYS/SP1/FPGA (M7_FPGA)                 Version: 15.1.2.11
423. /SYS/SPP0/FPGA (M7_FPGA)                Version: 15.1.2.11
435. /SYS/SPP1/FPGA (M7_FPGA)                Version: 15.1.2.11
447. /SYS/SPP2/FPGA (M7_FPGA)                Version: 15.1.2.11
459. /SYS/SPP3/FPGA (M7_FPGA)                Version: 15.1.2.11
477. /SYS/SWU0/FPGA (M7_FPGA)                Version: 6.2.0.2
502. /SYS/SWU1/FPGA (M7_FPGA)                Version: 6.2.0.2
527. /SYS/SWU2/FPGA (M7_FPGA)                Version: 6.2.0.2
552. /SYS/SWU3/FPGA (M7_FPGA)                Version: 6.2.0.2
577. /SYS/SWU4/FPGA (M7_FPGA)                Version: 6.2.0.2
602. /SYS/SWU5/FPGA (M7_FPGA)                Version: 6.2.0.2

Note : You can safely ignore any "idtxx_version call failed version=" messages in the above output.

Note that this information is also collected by ILOM Snapshot; in the ilom/@usr@local@bin@hw_version_-local.out file.

Example from an M7-8 server

-bash-4.1$ grep "M7_FPGA" ilom/@usr@local@bin@hw_version_-local.out
19. /SYS/CMIOU0/FPGA (M7_FPGA)               Version: 7.3.7.5
65. /SYS/CMIOU1/FPGA (M7_FPGA)               Version: 7.3.7.5
111. /SYS/CMIOU2/FPGA (M7_FPGA)              Version: 7.3.7.5
157. /SYS/CMIOU3/FPGA (M7_FPGA)              Version: 7.3.7.5
184. /SYS/SP0/FPGA (M7_FPGA)                 Version: 15.1.2.11

Example from an M7-16 server

-bash-4.1$ grep "M7_FPGA" ilom/*hw*
9. /SYS/SP0/FPGA (M7_FPGA)                  Version: 15.1.2.11
26. /SYS/SWU0/FPGA (M7_FPGA)                 Version: 6.2.0.2
51. /SYS/SWU1/FPGA (M7_FPGA)                 Version: 6.2.0.2
76. /SYS/SWU2/FPGA (M7_FPGA)                 Version: 6.2.0.2
101. /SYS/SWU3/FPGA (M7_FPGA)                Version: 6.2.0.2
126. /SYS/SWU4/FPGA (M7_FPGA)                Version: 6.2.0.2
151. /SYS/SWU5/FPGA (M7_FPGA)                Version: 6.2.0.2
-bash-4.1$ grep "/FPGA" spp_snapshot/*/ilom/*hw*
spp_snapshot/SPP0@SPM0/ilom/@usr@local@bin@hw_version_-local.out:19. /SYS/CMIOU0/FPGA (M7_FPGA)               Version: 7.3.7.5
spp_snapshot/SPP0@SPM0/ilom/@usr@local@bin@hw_version_-local.out:65. /SYS/CMIOU1/FPGA (M7_FPGA)               Version: 7.3.7.5
spp_snapshot/SPP0@SPM0/ilom/@usr@local@bin@hw_version_-local.out:105. /SYS/SPP0/FPGA (M7_FPGA)                Version: 15.1.2.11
spp_snapshot/SPP1@SPM0/ilom/@usr@local@bin@hw_version_-local.out: 1. /SYS/SPP1/FPGA (M7_FPGA)                 Version: 15.1.2.11
spp_snapshot/SPP1@SPM1/ilom/@usr@local@bin@hw_version_-local.out:19. /SYS/CMIOU4/FPGA (M7_FPGA)               Version: 7.3.7.5
spp_snapshot/SPP1@SPM1/ilom/@usr@local@bin@hw_version_-local.out:65. /SYS/CMIOU5/FPGA (M7_FPGA)               Version: 7.3.7.5
spp_snapshot/SPP2@SPM0/ilom/@usr@local@bin@hw_version_-local.out:19. /SYS/CMIOU8/FPGA (M7_FPGA)               Version: 7.3.7.5
spp_snapshot/SPP2@SPM0/ilom/@usr@local@bin@hw_version_-local.out:65. /SYS/CMIOU9/FPGA (M7_FPGA)               Version: 7.3.7.5
spp_snapshot/SPP2@SPM0/ilom/@usr@local@bin@hw_version_-local.out:105. /SYS/SPP2/FPGA (M7_FPGA)                Version: 15.1.2.11
spp_snapshot/SPP3@SPM0/ilom/@usr@local@bin@hw_version_-local.out: 1. /SYS/SPP3/FPGA (M7_FPGA)                 Version: 15.1.2.11
spp_snapshot/SPP3@SPM1/ilom/@usr@local@bin@hw_version_-local.out:19. /SYS/CMIOU12/FPGA (M7_FPGA)              Version: 7.3.7.5
spp_snapshot/SPP3@SPM1/ilom/@usr@local@bin@hw_version_-local.out:65. /SYS/CMIOU13/FPGA (M7_FPGA)              Version: 7.3.7.5

If several components are reporting downrev FPGA version compared to the following table then refer to the procedure available in point 4. below.

Platform Type	Component	FPGA Version
M7-16, M7-8 with one or 2 Pdoms	CMIOU	X.3.8.3
M7-16, M7-8 with one or 2 Pdoms	SP	15.1.3.4
M7-16	SPP	15.1.3.4
M7-16	SWU	Y.2.0.5

Where X and Y can be ignored.

In the context of a CMIOU replacement, please refer to the procedure described in point 3. below.

2. Obtain the firmware image from MOS

Log to My Oracle Support, from the Patches and Updates tab, "Patch Search" select "Product or Family (Advanced)".

Select the Product as SPARC M7-8 or M7-16 and from the Release list, select SPARC M7-8 or SPARC M7-16 HW Programmables 1.0.6.a.

Click Search and download the appropriate image.

HWP	Patch	FW revision	README File
1.0.6.a	26970558	X.3.8.3 / 15.1.3.4 / Y.2.0.5	README

Always refer to the associated README file for any specific instruction.

The downloaded zip file contains the .pkg file : Hardware_Programmables-1.0.6.a-SPARC_M7-Systems.pkg

This single .pkg file contains the FPGA images for all of the components (CMIOU, SWU and SP/SPP).

Place the firmware image on a server supporting one of the following protocols:
TFTP, FTP, SFTP, SCP, HTTP, or HTTPS.

3. Update CMIOU FPGA upon CMIOU replacement

When replacing a CMIOU in an M7-8 or M7-16 server, the new CMIOU is more likely running a downrev FPGA.

Replacing a CMIOU requires the respective physical domain to be off (stop /HOSTx).

The CMIOU FPGA update procedure can be performed with any other physical domains up and running.

3.1 CMIOU replacement

The CMIOU replacement procedure is described in M7-8 / M7-16 - How to replace a Faulty CMIOU in a CMIOU chassis (Doc ID 1951961.1).

Please follow the procedure to physically replace the CMIOU. This requires the respective host to be off.

After inserting the new CMIOU, you will see the following message in the event logs :

-> show /SP/logs/event/list/

Event
ID Date/Time Class Type Severity
----- ------------------------ -------- -------- --------
256 Tue Dec 15 07:21:23 2015 Chassis Log major
/SYS/CMIOU6/FPGA update required.
255 Tue Dec 15 07:21:19 2015 Chassis Action major
Hot insertion of /SYS/CMIOU6
254 Tue Dec 15 07:20:04 2015 Chassis Action major
Hot removal of /SYS/CMIOU6
253 Tue Dec 15 07:19:16 2015 IPMI Log minor
ID = b : 12/15/2015 : 07:19:16 : Slot/Connector : System Management Software : Ready for Device Removal : Asserted
252 Mon Dec 14 22:50:34 2015 System Log minor
Host ID 0: Standby
251 Mon Dec 14 22:50:31 2015 System Log minor
Host ID 0: Host stopped

The message basically confirms that an FPGA upgrade is required. You should proceed with the FPGA update.

3.2 FPGA update

To update the CMIOU FPGA, please follow the following procedure.

While the respective host is still off and the new CMIOU has been inserted, from the Active SP, apply the downloaded FPGA image by running

-> load -source http://n.n.n.n/Hardware_Programmables-1.0.6.a-SPARC_M7.pkg

The load command supports the following protocols : TFTP, FTP, SFTP, SCP, HTTP, or HTTPS.

The CMIOU FPGA update will take up to 15 minutes to complete. But the whole process will take more time to complete.

Do NOT power cycle any components until this script is reporting success.

Example :

-> load -source sftp://user@hostname//tmp/p22345376_106/Firmware/Hardware_Programmables/Hardware_Programmables-1.0.6.a-SPARC_M7-Systems.pkg
Enter remote user password: *********

NOTE: An upgrade takes several minutes to complete. ILOM
will enter a special mode to load new firmware. No
other tasks can be performed in ILOM until the
firmware upgrade is complete and ILOM is reset.

Are you sure you want to load the specified file (y/n)? y
2015-12-15 07:25:31 Install firmware package...
Version: 100.1.0.6
....Finish update of: FPGA Update v1.0.6 for M7.
************************************************************
WARNING: the script can take a very long time to finish.
(Up to 15 minutes per SP, SPP, CMIOU, and SWU board)
DO NOT INTERRUPT the script, it may result in a dead board.
************************************************************
2015-12-15 07:45:05 Found /SYS/SP0/SPM0, Active
2015-12-15 07:45:08 Found /SYS/SP1/SPM0, Standby
2015-12-15 07:45:13 Copying script to the SPMs...
2015-12-15 07:45:15 Copying FPGA image to the SPMs...
2015-12-15 07:46:24 Running FPGA update on /SYS/SP0/SPM0
2015-12-15 07:46:24 Running FPGA update on /SYS/SP1/SPM0
..............................................................................................................................................................................................
2015-12-15 08:02:16 /SYS/SP0/SPM0 : CMIOU6 FPGA update success
2015-12-15 08:02:16 /SYS/SP0/SPM0 : CMIOU0 FPGA verify success
2015-12-15 08:02:16 /SYS/SP0/SPM0 : CMIOU1 FPGA verify success
2015-12-15 08:02:16 /SYS/SP0/SPM0 : CMIOU2 FPGA verify success
2015-12-15 08:02:16 /SYS/SP0/SPM0 : CMIOU3 FPGA verify success
2015-12-15 08:02:17 /SYS/SP0/SPM0 : CMIOU4 FPGA verify success
2015-12-15 08:02:17 /SYS/SP0/SPM0 : CMIOU5 FPGA verify success
2015-12-15 08:02:17 /SYS/SP0/SPM0 : SP FPGA verify success
2015-12-15 08:02:17 /SYS/SP1/SPM0 : SP FPGA verify success
2015-12-15 08:02:17 FPGAs are at the latest revision.
2015-12-15 08:02:17 All done.
Finished updates

Firmware update is complete.
2015-12-15 08:02:28 Completed install

-> show /SP/logs/event/list/

Event
ID Date/Time Class Type Severity
----- ------------------------ -------- -------- --------
265 Tue Dec 15 08:02:17 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP1/SPM0 : SP FPGA success
264 Tue Dec 15 08:02:17 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : SP FPGA success
263 Tue Dec 15 08:02:17 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU5 FPGA success
262 Tue Dec 15 08:02:17 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU4 FPGA success
261 Tue Dec 15 08:02:17 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU3 FPGA success
260 Tue Dec 15 08:02:16 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU2 FPGA success
259 Tue Dec 15 08:02:16 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU1 FPGA success
258 Tue Dec 15 08:02:16 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU0 FPGA success
257 Tue Dec 15 08:02:16 2015 Firmware Update minor
Performing FPGA update on /SYS/SP0/SPM0 : CMIOU6 FPGA success

Note : If the command reports a failure, re-run the command. If the command fails again, contact Service and the owner of the SR.

At this point, the FPGA image has not yet been applied. A CMIOU power cycle is required. This can be done by unseating and reseating the CMIOU.

[(restricted_shell) sp0:~]# hw version | grep "M7_FPGA"
19. /SYS/CMIOU0/FPGA (M7_FPGA) Version: 7.3.8.3
65. /SYS/CMIOU1/FPGA (M7_FPGA) Version: 7.3.8.3
111. /SYS/CMIOU2/FPGA (M7_FPGA) Version: 7.3.8.3
157. /SYS/CMIOU3/FPGA (M7_FPGA) Version: 7.3.8.3
203. /SYS/CMIOU4/FPGA (M7_FPGA) Version: 7.3.8.3
249. /SYS/CMIOU5/FPGA (M7_FPGA) Version: 7.3.8.3
295. /SYS/CMIOU6/FPGA (M7_FPGA) Version: 7.3.7.5
335. /SYS/SP0/FPGA (M7_FPGA) Version: 15.1.3.4
347. /SYS/SP1/FPGA (M7_FPGA) Version: 15.1.3.4

As described below :

Prepare the CMIOU for removal.

-> set /System/DCUs/DCU_x/CMIOU_y action=prepare_to_remove

Verify that the CMIOU is ready to remove.

-> show /System/DCUs/DCU_x/CMIOU_y health

This should return the CMIOU as "Offline".

Verify that the blue Ready to Remove light on the CMIOU is on.
Unseat the CMIOU
- Pinch the latches on the backs of each ejector arms.
- Pull the ejector arms toward you to disengage the CMIOU connectors from the server.
- Grasp the ejector arms as close to the CMIOU as possible and pull the CMIOU one-third to half way out of the server
Wait 30 seconds
Reseat the CMIOU
- Slide the CMIOU back into the server until the levers begin to engage.
- Press the levers back together toward the center of the CMIOU, and then press the levers firmly against the CMIOU to fully seat it into the server. The levers should click into place when the module is fully seated in the server.

This procedure is also documented in the SPARC M7 Series Servers Service Manual.

After inserting the CMIOU, you may observe the following ereport. It can be ignored unless some faults are reported too.

2016-03-09/15:11:32 ereport.chassis.sensor.voltage-lnc-glo@/SYS/PDECB5
detector = /SYS/PDECB5/ECB/V_OUT
hidden = false
reading = 5.2
threshold = 10.64

EventID Date/Time Class Type Severity
----- ------------------------ -------- -------- --------
...
909 Wed Mar 9 15:14:35 2016 Chassis Action major Hot insertion of /SYS/CMIOU5
908 Wed Mar 9 15:14:28 2016 Sensor Log minor Voltage : /SYS/PDECB5/ECB/V_OUT : Lower Non-critical going high : reading 12.390 >= threshold 10.640 Volts
907 Wed Mar 9 15:11:38 2016 Chassis Action major Hot removal of /SYS/CMIOU5
906 Wed Mar 9 15:11:32 2016 Sensor Log minor Voltage : /SYS/PDECB5/ECB/V_OUT : Lower Non-critical going low : reading 5.180 < = threshold 10.640 Volts
905 Wed Mar 9 15:10:46 2016 IPMI Log minor ID = b : 03/09/2016 : 15:10:46 : Slot/Connector : System Management Software : Ready for Device Removal : Asserted
904 Wed Mar 9 15:04:40 2016 Firmware Update minor Performing FPGA verify on /SYS/SP1/SPM1 : CMIOU7 FPGA success
903 Wed Mar 9 15:04:39 2016 Firmware Update minor Performing FPGA update on /SYS/SP1/SPM1 : CMIOU5 FPGA success
902 Wed Mar 9 15:04:39 2016 Firmware Update minor Performing FPGA verify on /SYS/SP1/SPM0 : SP FPGA success
901 Wed Mar 9 15:04:39 2016 Firmware Update minor Performing FPGA verify on /SYS/SP0/SPM0 : SP FPGA success
900 Wed Mar 9 15:04:38 2016 Firmware Update minor Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU3 FPGA success
899 Wed Mar 9 15:04:38 2016 Firmware Update minor Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU0 FPGA success
898 Wed Mar 9 14:24:18 2016 Chassis Action major Hot insertion of /SYS/CMIOU5
897 Wed Mar 9 14:24:18 2016 Chassis Log major /SYS/CMIOU5/FPGA update required.
896 Wed Mar 9 14:16:13 2016 Chassis Action major Hot removal of /SYS/CMIOU5
...
873 Wed Mar 9 14:09:01 2016 IPMI Log minor ID = a : 03/09/2016 : 14:09:01 : Slot/Connector : System Management Software : Ready for Device Removal : Asserted

Note : In order to power cycle the component, after replacing the CMIOU, instead of unseating/reseating the CMIOU, it's also possible to power cycle the platform (by switching off/on the respective breakers on the rack). PDU breakers switch on/off sequences are described in the Service Manual:

Of course, this method will require all of the running hosts to be stopped and this will extend the maintenance window as the SP and/or SPP will reset.

Check from Restricted Shell that the CMIOU is now running the latest version

[(restricted_shell) sp0:~]# hw version | grep "M7_FPGA"
19. /SYS/CMIOU0/FPGA (M7_FPGA) Version: 7.3.8.3
65. /SYS/CMIOU1/FPGA (M7_FPGA) Version: 7.3.8.3
111. /SYS/CMIOU2/FPGA (M7_FPGA) Version: 7.3.8.3
157. /SYS/CMIOU3/FPGA (M7_FPGA) Version: 7.3.8.3
203. /SYS/CMIOU4/FPGA (M7_FPGA) Version: 7.3.8.3
249. /SYS/CMIOU5/FPGA (M7_FPGA) Version: 7.3.8.3
295. /SYS/CMIOU6/FPGA (M7_FPGA) Version: 7.3.8.3
381. /SYS/SP0/FPGA (M7_FPGA) Version: 15.1.3.4
393. /SYS/SP1/FPGA (M7_FPGA) Version: 15.1.3.4

And confirm from the above output that all of the CMIOUs are running the same FPGA version.

At this stage, the replaced component has been updated, the host can be restarted (start /HOSTx).

After restarting the host, you can observe the following in the event logs

795 Mon Jan 11 17:12:03 2016 System Log minor /SYS/CMIOU0/FPGA/FLASH update succeeded
794 Mon Jan 11 17:12:01 2016 System Log minor /SYS/CMIOU2/FPGA/FLASH update succeeded
793 Mon Jan 11 17:12:00 2016 System Log minor /SYS/CMIOU1/FPGA/FLASH update succeeded

3.3 No update required

When running the command, if no update is required, the command will just return as following :

-> load -source sftp://user@hostname/tmp/Hardware_Programmables-1.0.6.a-SPARC_M7-Systems.pkg
Enter remote user password: *********

NOTE: HOST0 is powered on; HOST0 firmware will be updated
automatically when HOST0 is restarted.

Are you sure you want to load the specified file (y/n)? y
2015-12-14 22:11:30 Install firmware package...
Version: 100.1.0.6
..Finish update of: FPGA Update v1.0.6 for M7.
************************************************************
WARNING: the script can take a very long time to finish.
(Up to 15 minutes per SP, SPP, CMIOU, and SWU board)
DO NOT INTERRUPT the script, it may result in a dead board.
************************************************************
2015-12-14 22:24:42 Found /SYS/SP0/SPM0, Active
2015-12-14 22:24:44 Found /SYS/SP1/SPM0, Standby
2015-12-14 22:24:50 Copying script to the SPMs...
2015-12-14 22:24:52 Copying FPGA image to the SPMs...
2015-12-14 22:26:08 Running FPGA update on /SYS/SP0/SPM0
2015-12-14 22:26:08 Running FPGA update on /SYS/SP1/SPM0
......................................................................................................................................................
2015-12-14 22:38:40 /SYS/SP0/SPM0 : CMIOU0 FPGA verify success
2015-12-14 22:38:40 /SYS/SP0/SPM0 : CMIOU1 FPGA verify success
2015-12-14 22:38:40 /SYS/SP0/SPM0 : CMIOU2 FPGA verify success
2015-12-14 22:38:40 /SYS/SP0/SPM0 : CMIOU3 FPGA verify success
2015-12-14 22:38:40 /SYS/SP0/SPM0 : CMIOU4 FPGA verify success
2015-12-14 22:38:40 /SYS/SP0/SPM0 : CMIOU5 FPGA verify success
2015-12-14 22:38:41 /SYS/SP0/SPM0 : CMIOU6 FPGA verify success
2015-12-14 22:38:41 /SYS/SP0/SPM0 : SP FPGA verify success
2015-12-14 22:38:41 /SYS/SP1/SPM0 : SP FPGA verify success
2015-12-14 22:38:41 FPGAs are at the latest revision.
2015-12-14 22:38:41 All done.
Finished updates

Firmware update is complete.
2015-12-14 22:38:54 Completed install

-> show /SP/logs/event/list/

Event
ID Date/Time Class Type Severity
----- ------------------------ -------- -------- --------
248 Mon Dec 14 22:38:41 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP1/SPM0 : SP FPGA success
247 Mon Dec 14 22:38:41 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : SP FPGA success
246 Mon Dec 14 22:38:41 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU6 FPGA success
245 Mon Dec 14 22:38:41 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU5 FPGA success
244 Mon Dec 14 22:38:40 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU4 FPGA success
243 Mon Dec 14 22:38:40 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU3 FPGA success
242 Mon Dec 14 22:38:40 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU2 FPGA success
241 Mon Dec 14 22:38:40 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU1 FPGA success
240 Mon Dec 14 22:38:40 2015 Firmware Update minor
Performing FPGA verify on /SYS/SP0/SPM0 : CMIOU0 FPGA success

4. Update FPGA for more than one component

If more than one component require FPGA update, the preferred method is probably to :

Stop all of the running hosts
From the Active SP, apply the downloaded FPGA image by running
-> load -source http://n.n.n.n/Hardware_Programmables-1.0.6.a-SPARC_M7.pkg

The load command supports the following protocols : TFTP, FTP, SFTP, SCP, HTTP, or HTTPS.

The update will take up to 15 minutes per SP, SPP, CMIOU, and SWU board. But the whole process will take more time to complete.

Do NOT power cycle any components until this script is reporting success.

Example :

-> load -source sftp://user@hostname//tmp/Hardware_Programmables-1.0.6.a-SPARC_M7-Systems.pkg
Enter remote user password: *********

NOTE: HOST0 is powered on; HOST0 firmware will be updated
automatically when HOST0 is restarted.

Are you sure you want to load the specified file (y/n)? y
2015-12-14 17:20:29 Install firmware package...
Version: 100.1.0.6
..Finish update of: FPGA Update v1.0.6 for M7.
************************************************************
WARNING: the script can take a very long time to finish.
(Up to 15 minutes per SP, SPP, CMIOU, and SWU board)
DO NOT INTERRUPT the script, it may result in a dead board.
************************************************************
2015-12-14 17:40:07 Found /SYS/SP0/SPM0, Stand-alone
2015-12-14 17:40:11 Copying script to the SPMs...
2015-12-14 17:40:12 Copying FPGA image to the SPMs...
2015-12-14 17:41:11 Running FPGA update on /SYS/SP0/SPM0
.....................................................................................................................................

..............................................................................................................................................................................................................................................

2015-12-14 18:34:48 /SYS/SP0/SPM0 : CMIOU0 FPGA update success
2015-12-14 18:34:48 /SYS/SP0/SPM0 : CMIOU1 FPGA update success
2015-12-14 18:34:48 /SYS/SP0/SPM0 : CMIOU2 FPGA update success
2015-12-14 18:34:48 /SYS/SP0/SPM0 : CMIOU3 FPGA update success
2015-12-14 18:34:49 /SYS/SP0/SPM0 : CMIOU4 FPGA update success
2015-12-14 18:34:49 /SYS/SP0/SPM0 : CMIOU5 FPGA update success
2015-12-14 18:34:49 /SYS/SP0/SPM0 : SP FPGA update success
2015-12-14 18:34:49 FPGAs are at the latest revision.
2015-12-14 18:34:49 All done.
Finished updates

Firmware update is complete.
2015-12-14 18:35:04 Completed install

Note : In the above, the 2 * "NOTE:" and message about ILOM and host restart are irrelevant as no SP or host reset is required

Note : If the command reports a failure, re-run the command. If the command fails again, contact Service and the owner of the SR.

-> show /SP/logs/event/list

Event
ID Date/Time Class Type Severity
----- ------------------------ -------- -------- --------
174 Mon Dec 14 18:34:49 2015 Firmware Update minor
Performing FPGA update on /SYS/SP0/SPM0 : SP FPGA success
173 Mon Dec 14 18:34:49 2015 Firmware Update minor
Performing FPGA update on /SYS/SP0/SPM0 : CMIOU5 FPGA success
172 Mon Dec 14 18:34:49 2015 Firmware Update minor
Performing FPGA update on /SYS/SP0/SPM0 : CMIOU4 FPGA success
171 Mon Dec 14 18:34:49 2015 Firmware Update minor
Performing FPGA update on /SYS/SP0/SPM0 : CMIOU3 FPGA success
170 Mon Dec 14 18:34:48 2015 Firmware Update minor
Performing FPGA update on /SYS/SP0/SPM0 : CMIOU2 FPGA success
169 Mon Dec 14 18:34:48 2015 Firmware Update minor
Performing FPGA update on /SYS/SP0/SPM0 : CMIOU1 FPGA success
168 Mon Dec 14 18:34:48 2015 Firmware Update minor
Performing FPGA update on /SYS/SP0/SPM0 : CMIOU0 FPGA success

At this point, the FPGA image has not yet been applied. A power cycle is required.

Power cycle the platform (by switching off/on the respective breakers on the rack). PDU breakers switch on/off sequences are described in the Service Manual:

When all of the SP/SPP are back online, check from Restricted Shell on the Active SP that the components is now running the latest version

[(restricted_shell) m7-16-sp:~]# hw version | grep "M7_FPGA"

And confirm from the above output that all of the components are running the latest FPGA versions.
The hosts can now be restarted
-> start /System
Are you sure you want to start all of the configured hosts on the system (y/n)? y

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