SPARC M5-32 and M6-32 Servers: Processor numbering and decoding CPU location.

Asset ID:	1-71-1540202.1
Update Date:	2017-10-11
Keywords:

Solution Type Technical Instruction Sure

Solution 1540202.1 : SPARC M5-32 and M6-32 Servers: Processor numbering and decoding CPU location.

Applies to:

SPARC M6-32 - Version All Versions to All Versions [Release All Releases]
SPARC M5-32 - Version All Versions to All Versions [Release All Releases]
Information in this document applies to any platform.

Goal

Solaris[TM] device paths and messaging reference the ID of a given processor (in /var/adm/messages, console logs, core files, OBP probing, FMA logs etc.).

This document provides the cpuid cheat sheets for the SPARC M5-32 and M6-32 Servers.

By correctly mapping this ID to a physical location, we know that we are servicing the right component to resolve a hardware problem. An incorrect mapping could result in replacing and/or servicing the wrong component and could cause further outages or problems on the platform.
Also, on a sun4v architecture such as the M5-32 or M6-32 platform, this may help to understand how the cpus are assigned to the various domains.

When FMA indicts an component, the decoding is obviously automatically done and the indicted CMP or CMU is the one to be serviced.

Solution

Reminder :
An M5-32 or M6-32 server is composed of up to 32x SPARC M5 or M6 3.6GHz CPUs.

Each SPARC M5 is composed of 6 S3 cores.
Each SPARC M6 is composed of 12 S3 cores.

An M5-32 can therefore have up to 192 cores.
An M6-32 can therefore have up to 384 cores.

Each S3 cores has 8 threads/strands (48 threads per SPARC M5 - 96 threads per SPARC M6).
An M5-32 can therefore have up to 1536 threads.
An M6-32 can therefore have up to 3072 threads.

A CPU memory board Unit (CMU) is equipped with two SPARC M5 or SPARC M6 CPU modules.
A SPARC M5 CMU has 12 cores, 96 threads.
A SPARC M6 CMU has 24 cores, 192 threads.

Note : The SPARC M6 CMU can be installed in a M5-32 server but all CMUs in a DCU must be the same type.

A Domain Configuration Unit (DCU) is grouping 2 to 4 CMUs for non-bounded domain (expandable = true).

A bounded domain (expandable = false) can have a minimum of one CMU.

A Physical Domain is composed of one to four DCUs.

A configuration with 5 or 7 CMPs active in a DCU is not supported. In configurations where a DCU has only two CMUs, individual CMPs can be unconfigured. In configurations where a DCU has three or four CMUs, an entire CMU will be unconfigured if a CMP needs to be reconfigured.

It's important to note that the CPU identification is done based on two different references :
- ILOM, Hostconfig, POST are using the socket ids which is derived based on the physical chip location,
- Hypervisor, OBP, Solaris, FMA are using the node ids which is derived from the Scalability Links connectivity.

The Socket to Node id basic translation is as following

Socket ID	Node ID
0	0
1	1
2	4
3	5
4	2
5	3
6	6
7	7

See the attached spreadsheet for a complete mapping of the CPU identification and respective commands :

Note : It must be noted that when the expandable setting (from ILOM) for the respective Pdom is set to false (the Pdom is then composed of only one DCU) then the CPU mapping as reported by ldm will start from 0 (CID, PID, CPUSET) whatever the DCU number assigned to the host/Pdom. The information and CPU numbering as reported by Solaris (VCPU, prtdiag, prtpicl, psrinfo) will be consistent whatever the expandable variable setting. See Below

ILOM :

From an ILOM perspective, each CMU (CMU[0-15]) has 2 CMPs (CMP[0-1]). The NAC format for the SPARC M5 and SPARC M6 as visible from the ILOM shell is:

/System/Processors/CPUs/CPU_[0-31]
/SYS/CMU[0-15]/CMP[0-1]

Example

-> show -d properties /System/Processors/CPUs/CPU_15
/System/Processors/CPUs/CPU_15
    Properties:
        health = OK
        health_details = -
        requested_state = Enabled
        part_number = Not Available
        serial_number = Not Available
        location = CMU7/CMP1 (Processor Board 7 Host Processor 1)
        model = Not Available
        max_clock_speed = Not Available
        total_cores = Not Available
        enabled_cores = 12
        temperature = Not Available

-> show -d properties /SYS/CMU7/CMP1
/SYS/CMU7/CMP1
    Properties:
        type = Host Processor
        ipmi_name = /CPU15
        requested_config_state = Enabled
        current_config_state = Enabled
        disable_reason = None

The NAC format for the S3 cores as visible from the ILOM shell is :
- for SPARC M5 /SYS/CMU[0-15]/CMP[0-1]/CORE[0,2,4,6,8,10]
- for SPARC M6 /SYS/CMU[0-15]/CMP[0-1]/CORE[0,1,2,3,4,5,6,7,8,9,10,11]

Each DCU (DCU[0-3]) is composed of the following CMU/CMP :

DCU	NAC Name	ipmi_name	SDM
DCU0	/SYS/CMU[0-3]/CMP[0-1]	/CPU[0-7]	/System/Processors/CPUs/CPU_[0-7]
DCU1	/SYS/CMU[4-7]/CMP[0-1]	/CPU[8-15]	/System/Processors/CPUs/CPU_[8-15]
DCU2	/SYS/CMU[8-11]/CMP[0-1]	/CPU[16-23]	/System/Processors/CPUs/CPU_[16-23]
DCU3	/SYS/CMU[12-15]/CMP[0-1]	/CPU[24-31]	/System/Processors/CPUs/CPU_[24-31]

You can obtain a summary of the chassis configuration as following :

-> show /System/Processors summary_description

/System/Processors
Properties:
summary_description = Sixteen Oracle SPARC M6

OBP Device tree :

As soon as the Host has been started and OBP is running, the CPUIDs are visible in hexadecimal format as following :

{0} ok ls /
f02a087c cpu@2cf
… [output omitted]
f028c6ac cpu@10
f028c57c cpu@f
f028c44c cpu@e
… [output omitted]
f028b60c cpu@2
f028b4dc cpu@1
f028b3ac cpu@0

The values in hexadecimal do match the decimal CPUID values reported from Solaris.

Example :

{0} ok cd cpu@6c
{0} ok .properties
clock-frequency          d6924470
compatible               SPARC-M6
                         SPARC-M5
                         SPARC-M4
                         SUNW,sun4v-cpu
                         sun4v
device_type              cpu
reg                      c000006c 00000000 00000000 00000000
name                     cpu

Similar information available from the 'prtconf -vp' output

Example :

    Node 0xf028b3bc
        clock-frequency: d6924470
        compatible: 'SPARC-M6' + 'SPARC-M5' + 'SPARC-M4' + 'SUNW,sun4v-cpu' + 'sun4v'
        device_type: 'cpu'
        reg: c0000000.00000000.00000000.00000000
        name: 'cpu'

The prtpicl output might help to provide some more details and the a reference to the CPU thread id :

Example :

         cpu (cpu, 2780000091d)
          :StateBegin    Thu Oct 3 09:37:54 2013
          :FPUType       sparcv9
          :ProcessorType         sparcv9
          :State         on-line
          :ID    108
          :dtlb-entries 128
          :itlb-entries 64
          :l1-dcache-line-size   32
          :l1-dcache-size        16384
          :l1-dcache-associativity       4
          :l3-cache-line-size    64
          :l3-cache-size         50331648
          :l3-cache-associativity        12
          :l2-cache-line-size    32
          :l2-cache-size         131072
          :l2-cache-associativity        8
          :l1-icache-line-size   32
          :l1-icache-size        16384
          :l1-icache-associativity       4
          :portid        108
          :cpuid         108
          :UnitAddress   c000006c,0
          :reg   c0 00 00 6c 00 00 00 00 00 00 00 00 00 00 00 00
          :device_type   cpu
          :compatible   (27800000925TBL)
           | SPARC-M6 |
           | SPARC-M5 |
           | SPARC-M4 |
           | SUNW,sun4v-cpu |
           | sun4v |
          :clock-frequency       0xd6924470
          :devfs-path    /cpu
          :binding-name cpu
          :instance      -1
          :_class        cpu
          :name cpu

Solaris :

From Solaris, CPU identification is based on the Node ids as described before.
The M5-32 and M6-32 server is a sun4v architecture. Which means that each Physical domain can run several Logical domains.
The global number of Virtual CPU available to a PDomain will be the sum of the VCPUs assigned to each domain.
If no guest domains are configured or active , the primary domain will have all of the CPUs.

The processor IDs can be displayed from Solaris via the following commands with the associated definitions :

psrinfo
- chipid : refers to the SPARC M5 or SPARC M6 chip used in the domain. This is an incremented value with no relationship with thread ID or PID.
- virtual processor : the virtual CPU ids refer to the CPU thread id.
prtdiag
- CPU ID : the virtual CPU ids refer to the CPU thread id.
prtpicl
- portid/cpuid/UnitAddress : CPU thread id in decimal and hexadecimal format.
fmtopo
- cpuboard : CMU
- chip : node ID
- core : core ID
- strand/cpuid : physical CPU ID
ldm
- CID is the Core ID from which you can determine the physical location,
- the VCPU ID as available in the psrinfo/prtdiag output from the guest domain, this refers to the CPU thread,
- PID/CPUSET : physical CPU/CPU set ID.

The fmtopo output provides provides good mix for both logical and physical information.

Example :

hc://:chassis-mfg=Oracle Corporation:chassis-name=SPARC M5-32:chassis-part=P0.1d:M4-32:chassis-serial=m4-32-037/chassis=0/cpuboard=2/chip=3/core=58/strand=464
group: protocol                       version: 1   stability: Private/Private
    resource          fmri      hc://:chassis-mfg=Oracle Corporation:chassis-name=SPARC M5-32:chassis-part=P0.1d:M4-32:chassis-serial=m4-32-037/chassis=0/cpuboard=2/chip=3/core=58/strand=464
    FRU               fmri      hc://:chassis-mfg=Oracle Corporation:chassis-name=SPARC M5-32:chassis-part=P0.1d:M4-32:chassis-serial=m4-32-037:fru-serial=465769T+1203JP009R:fru-part=07011250:fru-revision=08/chassis=0/cpuboard=2
    label             string    /SYS/CMU2
    ASRU              fmri      cpu:///cpuid=464/serial=10441660c10002e5
group: authority                      version: 1   stability: Private/Private
    chassis-mfg       string    Oracle Corporation
    chassis-name      string    SPARC M5-32
    chassis-part      string    P0.1d:M4-32
    chassis-serial    string    m4-32-037
group: system                         version: 1   stability: Private/Private
    isa               string    sparc
    machine           string    sun4v

hc://:chassis-mfg=Oracle Corporation:chassis-name=SPARC M6-32:chassis-part=31994685+1+1:chassis-serial=AK00136495/chassis=0/cpuboard=0/chip=0/core=0/strand=0
group: protocol                       version: 1   stability: Private/Private
    resource          fmri      hc://:chassis-mfg=Oracle Corporation:chassis-name=SPARC M6-32:chassis-part=31994685+1+1:chassis-serial=AK00136495/chassis=0/cpuboard=0/chip=0/core=0/strand=0
    FRU               fmri      hc://:chassis-mfg=Oracle Corporation:chassis-name=SPARC M6-32:chassis-part=31994685+1+1:chassis-serial=AK00136495:fru-serial=465769T+1325FE00KC:fru-part=7070507:fru-revision=01/chassis=0/cpuboard=0
    label             string    /SYS/CMU0
    ASRU              fmri      cpu:///cpuid=0/serial=9c30889208002e3
group: authority                      version: 1   stability: Private/Private
    chassis-mfg       string    Oracle Corporation
    chassis-name      string    SPARC M6-32
    chassis-part      string    31994685+1+1
    chassis-serial    string    AK00136495
group: system                         version: 1   stability: Private/Private
    isa               string    sparc
    machine           string    sun4v

The 'ldm' command and 'list-devices' subcommands (core, cpu) is probably the best way to figure out the layout.

For instance, a PDomain composed of DCU0 (CMU0, CMU1, CMU2, CMU3) so 4 (CMU) x 2 (M5) x 6 (cores) x 8 (threads) = 384 with a primary and 3 guest domains :

% ldm list
NAME             STATE      FLAGS   CONS    VCPU MEMORY   UTIL NORM UPTIME
primary          active     -n-cv- UART    324   1022720M 0.2% 0.0% 1d 17h 17m
gd0              active     -n---- 5000    20    8G       0.0% 0.0% 16h 37m
gd1              active     -t---- 5001    20    8G       5.0% 5.0% 16h 37m
gd2              active     -t---- 5002    20    8G       5.0% 5.0% 16h 37m

The number of VPUs assigned to the LDOMs will match the psrinfo output.

primary% psrinfo | wc -l
324
gd1% psrinfo | wc -l
20

The cpuids as observed from the primary (control) domain may be different from the cpuids observed from the guest domains.
The only way to determine which CPUs are used is to use the 'ldm' command output from the primary domain.

Note : the CPU thread ids for a Guest domain always starts from zero. So either CID or CPUSET/PID must be used to determine the physical location.

From the primary domain :

To determine the primary domain configuration :

pd0% ldm list -l primary
NAME             STATE      FLAGS   CONS    VCPU MEMORY   UTIL NORM UPTIME
primary          active     -n-cv- UART    324   1022720M 0.2% 0.0% 1d 17h 52m
...
CORE
    CID    CPUSET
    0      (0, 1, 2, 3, 4, 5, 6, 7)
    2      (16, 17, 18, 19, 20, 21, 22, 23)
   ...
    10     (80, 81, 82, 83, 84, 85, 86, 87)
    16     (128, 129, 130, 131, 132, 133, 134, 135)
   …
    26     (208, 209, 210, 211, 212, 213, 214, 215)
    32     (256, 257, 258, 259, 260, 261, 262, 263)
    ...
    42     (336, 337, 338, 339, 340, 341, 342, 343)
    48     (384, 385, 386, 387, 388, 389, 390, 391)
    ...
    58     (464, 465, 466, 467, 468, 469, 470, 471)
    64     (512, 513, 514, 515, 516, 517, 518, 519)
    ...
    74     (592, 593, 594, 595, 596, 597, 598, 599)
    80     (640, 641, 642, 643, 644, 645, 646, 647)
    ...
    90     (720, 721, 722, 723, 724, 725, 726, 727)
    96     (768, 769, 770, 771, 772, 773, 774, 775)
    ...
    104    (832, 833, 834, 835)

VCPU
    VID    PID    CID    UTIL NORM STRAND
    0      0      0      5.2% 0.1%   100%
    1      1      0      5.8% 0.2%   100%
    2      2      0      4.0% 0.1%   100%
    3      3      0      0.6% 0.0%   100%
    4      4      0      0.3% 0.0%   100%
    5      5      0      0.2% 0.0%   100%
    6      6      0      0.2% 0.0%   100%
    7      7      0      0.5% 0.0%   100%
    8      16     2      0.2% 0.0%   100%
    …
    15     23     2      0.2% 0.0%   100%
    16     32     4      0.2% 0.0%   100%
    ...
    23     39     4      0.2% 0.0%   100%
    24     48     6      0.2% 0.0%   100%
    ...
    31     55     6      0.2% 0.0%   100%
    32     64     8      0.2% 0.0%   100%
    ...
    39     71     8      0.2% 0.0%   100%
    ...
    606    822    102    0.1% 0.0%   100%
    607    823    102    0.0% 0.0%   100%
    608    832    104    0.0% 0.0%   100%
    609    833    104    0.0% 0.0%   100%
    610    834    104    0.0% 0.0%   100%
    611    835    104    0.0% 0.0%   100%

To determine the guest domain configuration :

pd0% ldm list -l gd2
NAME             STATE      FLAGS   CONS    VCPU MEMORY   UTIL NORM UPTIME
gd2              active     -n---- 5002    20    8G       0.2% 0.0% 20m
...
CORE
    CID    CPUSET
    104    (836, 837, 838, 839)
    106    (848, 849, 850, 851, 852, 853, 854, 855)
    112    (896, 897, 898, 899, 900, 901, 902, 903)
VCPU
    VID    PID    CID    UTIL NORM STRAND
    0      836    104    1.0% 0.1%   100%
    1      837    104    0.1% 0.0%   100%
    2      838    104    0.0% 0.0%   100%
    3      839    104    0.1% 0.0%   100%
    4      848    106    0.2% 0.0%   100%
    5      849    106    0.2% 0.0%   100%
    6      850    106    0.0% 0.0%   100%
    7      851    106    0.2% 0.0%   100%
    8      852    106    0.3% 0.0%   100%
    9      853    106    0.2% 0.0%   100%
    10     854    106    0.0% 0.0%   100%
    11     855    106    0.2% 0.0%   100%
    12     896    112    0.0% 0.0%   100%
    13     897    112    0.0% 0.0%   100%
    14     898    112    0.0% 0.0%   100%
    15     899    112    0.0% 0.0%   100%
    16     900    112    0.0% 0.0%   100%
    17     901    112    0.0% 0.0%   100%
    18     902    112    0.0% 0.0%   100%
    19     903    112    0.0% 0.0%   100%

From a guest domain :

The VCPUs are logically assigned to the guest domains.
From a guest domain, there is no way to physically locate where the VCPUs are.
This information must be checked from the primary domain.
The psrinfo -vp would only provide information about the composition in term of M5 chips and cores being used.

gd2% psrinfo -vp
The physical processor has 2 cores and 12 virtual processors (0-11)
The core has 4 virtual processors (0-3)
The core has 8 virtual processors (4-11)
    SPARC-M5 (chipid 0, clock 3333 MHz)
The physical processor has 1 core and 8 virtual processors (12-19)
The core has 8 virtual processors (12-19)
    SPARC-M5 (chipid 1, clock 3333 MHz)
gd2% prtdiag -v
System Configuration: Oracle Corporation sun4v SPARC M5-32
Memory size: 8 Gigabytes

================================ Virtual CPUs ================================

CPU ID Frequency Implementation         Status
------ --------- ---------------------- -------
0      3333 MHz SPARC-M5               on-line
1      3333 MHz SPARC-M5               on-line
2      3333 MHz SPARC-M5               on-line
3      3333 MHz SPARC-M5               on-line
4      3333 MHz SPARC-M5               on-line
5      3333 MHz SPARC-M5               on-line
6      3333 MHz SPARC-M5               on-line
7      3333 MHz SPARC-M5               on-line
8      3333 MHz SPARC-M5               on-line
9      3333 MHz SPARC-M5               on-line
10     3333 MHz SPARC-M5               on-line
11     3333 MHz SPARC-M5               on-line
12     3333 MHz SPARC-M5               on-line
13     3333 MHz SPARC-M5               on-line
14     3333 MHz SPARC-M5               on-line
15     3333 MHz SPARC-M5               on-line
16     3333 MHz SPARC-M5               on-line
17     3333 MHz SPARC-M5               on-line
18     3333 MHz SPARC-M5               on-line
19     3333 MHz SPARC-M5               on-line

Example :

The following example is from a Pdomain composed of DCU2 (CMU8, CMU9, CMU10, CMU11) where CMU8 is degraded.
From the primary domain, we can see that 2 LDOMs exist and are active with a total of 284 threads.

pd2% ldm list
NAME             STATE      FLAGS   CONS    VCPU MEMORY   UTIL NORM UPTIME
primary          active     -n-cv- UART    248   768768M 0.4% 0.0% 10h 54m
gd0              active     -n---- 5000    16    8G       0.1% 0.0% 36m
gd1              active     -t---- 5001    20    8G       5.0% 5.0% 52m

The primary domain is composed of /SYS/CMU9/CMP0, /SYS/CMU9/CMP1, /SYS/CMU10/CMP0, /SYS/CMU10/CMP1, /SYS/CMU11/CMP0, /SYS/CMU11/CMP1/CORE0

pd2% ldm list -l | more
NAME             STATE      FLAGS   CONS    VCPU MEMORY   UTIL NORM UPTIME
primary          active     -n-cv- UART    248   768768M 0.3% 0.0% 10h 56m
…
CORE
    CID    CPUSET
    288    (2304, 2305, 2306, 2307, 2308, 2309, 2310, 2311)
    ...
    298    (2384, 2385, 2386, 2387, 2388, 2389, 2390, 2391)
    304    (2432, 2433, 2434, 2435, 2436, 2437, 2438, 2439)
    ...
    314    (2512, 2513, 2514, 2515, 2516, 2517, 2518, 2519)
    320    (2560, 2561, 2562, 2563, 2564, 2565, 2566, 2567)
    …
    336    (2688, 2689, 2690, 2691, 2692, 2693, 2694, 2695)
    338    (2704, 2705, 2706, 2707, 2708, 2709, 2710, 2711)
    ...
    346    (2768, 2769, 2770, 2771, 2772, 2773, 2774, 2775)
    352    (2816, 2817, 2818, 2819, 2820, 2821, 2822, 2823)
    ...
    368    (2944, 2945, 2946, 2947, 2948, 2949, 2950, 2951)

VCPU
    VID    PID    CID    UTIL NORM STRAND
    1728   2304   288    5.5% 0.2%   100%
   ...
    2215   2951   368    1.2% 1.0%   100%

…

The Guest domain gd0 is composed of 16 threads from /SYS/CMU11/CMP1/CORE8 and /SYS/CMU11/CMP1/CORE10

NAME             STATE      FLAGS   CONS    VCPU MEMORY   UTIL NORM UPTIME
gd0              active     -n---- 5000    16    8G       0.1% 0.0% 38m

CORE
    CID    CPUSET
    376    (3008, 3009, 3010, 3011, 3012, 3013, 3014, 3015)
    378    (3024, 3025, 3026, 3027, 3028, 3029, 3030, 3031)

VCPU
    VID    PID    CID    UTIL NORM STRAND
    0      3008   376    0.5% 0.1%   100%
    1      3009   376    0.0% 0.0%   100%
    2      3010   376    0.1% 0.0%   100%
    3      3011   376    0.1% 0.0%   100%
    4      3012   376    0.1% 0.1%   100%
    5      3013   376    0.0% 0.0%   100%
    6      3014   376    0.0% 0.0%   100%
    7      3015   376    0.0% 0.0%   100%
    8      3024   378    0.0% 0.0%   100%
    9      3025   378    0.1% 0.0%   100%
    10     3026   378    0.1% 0.0%   100%
    11     3027   378    0.1% 0.0%   100%
    12     3028   378    0.0% 0.0%   100%
    13     3029   378    0.1% 0.0%   100%
    14     3030   378    0.1% 0.0%   100%
    15     3031   378    0.0% 0.0%   100%

…

The Guest domain gd1 is composed of 16 threads from /SYS/CMU11//CMP1/CORE2, /SYS/CMU11//CMP1/CORE4 and 4 threads from /SYS/CMU11//CMP1/CORE6.

NAME             STATE      FLAGS   CONS    VCPU MEMORY   UTIL NORM UPTIME
gd1              active     -t---- 5001    20    8G       5.0% 5.0% 54m

...

CORE
    CID    CPUSET
    370    (2960, 2961, 2962, 2963, 2964, 2965, 2966, 2967)
    372    (2976, 2977, 2978, 2979, 2980, 2981, 2982, 2983)
    374    (2992, 2993, 2994, 2995)

VCPU
    VID    PID    CID    UTIL NORM STRAND
    0      2960   370    100% 100%   100%
    1      2961   370    0.0% 0.0%   100%
    2      2962   370    0.0% 0.0%   100%
    3      2963   370    0.0% 0.0%   100%
    4      2964   370    0.0% 0.0%   100%
    5      2965   370    0.0% 0.0%   100%
    6      2966   370    0.0% 0.0%   100%
    7      2967   370    0.0% 0.0%   100%
    8      2976   372    0.0% 0.0%   100%
    9      2977   372    0.0% 0.0%   100%
    10     2978   372    0.0% 0.0%   100%
    11     2979   372    0.0% 0.0%   100%
    12     2980   372    0.0% 0.0%   100%
    13     2981   372    0.0% 0.0%   100%
    14     2982   372    0.0% 0.0%   100%
    15     2983   372    0.0% 0.0%   100%
    16     2992   374    0.0% 0.0%   100%
    17     2993   374    0.0% 0.0%   100%
    18     2994   374    0.0% 0.0%   100%
    19     2995   374    0.0% 0.0%   100%

Note about expandable = false :

When the expandable variable for the respective Pdom is set to false (only one DCU in the Pdom) from ILOM then the numbering as reported by the ldm command will differ.

Only the CID, CPUSET, PID and also the fmtopo output numbering will differ. Other information from Solaris (prtdiag, psrinfo ..) and VCPUID do not differ.

This must be considered accordingly when decoding the cpu numbering.

Examples :

Host3 is composed of DCU#3 with expandable=true

ldm reports

CORE
    CID    CPUSET
    384    (3072, 3073, 3074, 3075, 3076, 3077, 3078, 3079)
    386    (3088, 3089, 3090, 3091, 3092, 3093, 3094, 3095)

...

VCPU
    VID    PID    CID    UTIL NORM STRAND
    2304   3072   384    1.2% 0.4%   100%
    2305   3073   384    0.9% 0.3%   100%

prtdiag reports

CPU ID Frequency Implementation         Status
------ --------- ---------------------- -------
2304   3600 MHz SPARC-M5               on-line
2305   3600 MHz SPARC-M5               on-line
2306   3600 MHz SPARC-M5               on-line

...

psrinfo reports

The physical processor has 6 cores and 48 virtual processors (2304-2351)
The core has 8 virtual processors (2304-2311)
The core has 8 virtual processors (2312-2319)
The core has 8 virtual processors (2320-2327)
The core has 8 virtual processors (2328-2335)
The core has 8 virtual processors (2336-2343)
The core has 8 virtual processors (2344-2351)
...

prtpicl reports

          :ID    2304
          :portid        2304
          :cpuid         2304
          :ID    2305
          :portid        2305
          :cpuid         2305

fmtopo reports

hc://:chassis-mfg=Oracle Corporation:chassis-name=SPARC M5-32:chassis-part=31486290+1+1:chassis-serial=AK00087872/chassis=0/cpuboard=12/chip=24/core=384/stra
nd=3072
    resource          fmri      hc://:chassis-mfg=Oracle Corporation:chassis-name=SPARC M5-32:chassis-part=31486290+1+1:chassis-serial=AK00087872/chassis=0/c
puboard=12/chip=24/core=384/strand=3072
    label             string    /SYS/CMU12
    ASRU              fmri      cpu:///cpuid=3072/serial=9491888e10002e3

Host3 is composed of DCU#3 with expandable=false

ldm reports

CORE
    CID    CPUSET
    0      (0, 1, 2, 3, 4, 5, 6, 7)
    2      (16, 17, 18, 19, 20, 21, 22, 23)

...

VCPU
    VID    PID    CID    UTIL NORM STRAND
    2304   0      0      1.3% 0.5%   100%
    2305   1      0      2.4% 1.9%   100%

prtdiag reports

psrinfo reports

prtpicl reports

:ID    2304
          :portid        2304
          :cpuid         2304
          :ID    2305
          :portid        2305
          :cpuid         2305

fmtopo reports

hc://:chassis-mfg=Oracle Corporation:chassis-name=SPARC M5-32:chassis-part=31486290+1+1:chassis-serial=AK00087872/chassis=0/cpuboard=0/chip=0/core=0/strand=0
    resource          fmri      hc://:chassis-mfg=Oracle Corporation:chassis-name=SPARC M5-32:chassis-part=31486290+1+1:chassis-serial=AK00087872/chassis=0/c
puboard=0/chip=0/core=0/strand=0
    label             string    /SYS/CMU12
    ASRU              fmri      cpu:///cpuid=0/serial=9491888e10002e3

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