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Asset ID: 1-71-1017499.1
Update Date:2015-04-13
Keywords:
Solution Type  Technical Instruction Sure

Solution  1017499.1 :   Sun Fire[TM] 3800/48x0/6800/E4900/E6900/E2900/V1280 and Netra[TM] 1280/1290 server: Understanding Memory Interleaving  

Related Items 
    

  • Sun Fire 3800 Server
    •  
  • Sun Fire 6800 Server
    •  
  • Sun Fire 4810 Server
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  • Sun Fire 4800 Server
    •  
Related Categories 
    

  • PLA-Support>Sun Systems>SPARC>Enterprise>SN-SPARC: Exx00
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  • _Old GCS Categories>Sun Microsystems>Servers>Midrange Servers
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PreviouslyPublishedAs
228626 


Applies to:  

Sun Fire 3800 Server - Version All Versions and later
Sun Fire 4800 Server - Version All Versions and later
Sun Fire 4810 Server - Version All Versions and later
Sun Fire 6800 Server - Version All Versions and later
All Platforms



Goal


*Goal
Enter the goal of the document. What does the customer want to accomplish?


Explains the different memory interleaving options and shows lot of examples.


 


Solution


Each physical bank (4 DIMMS) of memory has 2 logical banks.


    

  • 

    Physical bank 0 contains 2 logical banks, L0 & L2
    

    • 

  • 

    Physical bank 1 contains 2 logical banks, L1 & L3
    

    • 



The 1st logical bank is the front of all 4 DIMMS


The 2nd logical bank is the back of all 4 DIMMS


Memory interleaving, interleaves logical banks together.


---------------------------------------------------------------------
       Pictorial representation of physical bank 0's 4 DIMMs
---------------------------------------------------------------------
         Logical bank L0                     Logical bank L2
         Front of DIMM                       Back of DIMM
   ---------------------------         ---------------------------
   |    O   O  O   O   O     |         |    O   O  O   O   O     |
   |      O   O  O   O       |         |      O   O  O   O       |
   |    9 16bit drams        |         |    9 16bit drams        |
   ------------U--------------         ------------U-------------- 
         Front of DIMM                       Back of DIMM
   ---------------------------         ---------------------------
   |    O   O  O   O   O     |         |    O   O  O   O   O     |
   |      O   O  O   O       |         |      O   O  O   O       |
   |    9 16bit drams        |         |    9 16bit drams        |
   ------------U--------------         ------------U-------------- 
         Front of DIMM                       Back of DIMM
   ---------------------------         ---------------------------
   |    O   O  O   O   O     |         |    O   O  O   O   O     |
   |      O   O  O   O       |         |      O   O  O   O       |
   |    9 16bit drams        |         |    9 16bit drams        |
   ------------U--------------         ------------U-------------- 
         Front of DIMM                       Back of DIMM
   ---------------------------         ---------------------------
   |    O   O  O   O   O     |         |    O   O  O   O   O     |
   |      O   O  O   O       |         |      O   O  O   O       |
   |    9 16bit drams        |         |    9 16bit drams        |
   ------------U--------------         ------------U-------------- 
---------------------------------------------------------------------


Below is a top view of 4 DIMMS (1 physical bank or 2 logical banks).


To get the logical bank size, simply add up all the front or backs: 128mb+128mb+128mb+128mb = 512mb logical bank size.


---------------------------------------------------------------------
 Top view of 4 DIMMs;  Each DIMM is 256mb size (128mb, front/back). 
---------------------------------------------------------------------
          128MB                          Front
          ==============256MB DIMM============     DIMM 0
          128MB                          Back

          128MB                          Front
          ==============256MB DIMM============     DIMM 1
          128MB                          Back

          128MB                          Front
          ==============256MB DIMM============     DIMM 2
          128MB                          Back

          128MB                          Front
          ==============256MB DIMM============     DIMM 3
          128MB                          Back
--------------------------------------------------------------------- 


Some technical details:


    

  • A cache line is 576 bits. 
    • 

      

    • 576bits/8 = 72 bytes
      • 

    

  • 576/16 bit drams = 36 drams
    • 

  • 4 DIMM halves (front) X 9 DRAMS = 36 drams = 1 logical bank
    • 

      

    • 9 drams X 16 bits = 144 bits on front/back of each dimm
      • 

    

  • 144 bits X 4 dimms = 576 bits
    • 



...and more:


    

  • 1 physical bank (2 logical banks) can only transfer 9 bytes at a time.
    • 

      

    • 9 bytes X 8 bits = 72 bits
      • 

    • 9 drams X 8 sides ( 4 DIMMS) = 72 bits
      • 

    

  • Each logical bank is accessed every other time; This is 2-way interleaving
    • 



...and still more:


    

  • 8 physical banks (16 logical banks) can transfer 576 bits at a time
    • 

      

    • 9 drams X 64 sides ( 32 DIMMS ) = 576 bits
      • 

    

  • Each logical bank is accessed every 16th time; This is 16-way interleaving
    • 



There are 2 memory interleave settings:


   interleave-scope = within-cpu
                      within-board
                      across-boards

   interleave-mode = off 
                     fixed    (only interleave DIMMS of the same size)
                     optimal    (interleave DIMMS of different sizes)


Example 1


     interleave-scope = within-cpu
     interleave-mode = optimal


Looking at interleave segment 0 from a prtdiag example:


 
                     Logical  Logical  Logical
               Port  Bank     Bank     Bank     DIMM    Interleave  Interleave 
FRU Name        ID   Num      Size     Status   Size    Factor      Segment 
-------------  ----  ----     ------   -------  ------  ----------  ---------- 
/N0/SB0/P0/B0    0    0       512MB    pass      256MB     4-way       0 
/N0/SB0/P0/B1    0    1       512MB    pass      256MB     4-way       0 
/N0/SB0/P0/B0    0    2       512MB    pass      256MB     4-way       0 
/N0/SB0/P0/B1    0    3       512MB    pass      256MB     4-way       0 


We have 2 physical banks, so 4 logical banks. Logical bank 0 is the front of DIMMS in physical bank 0 shown below:


/N0/SB0/P0/B0/D0  J13300
/N0/SB0/P0/B0/D1  J13400 
/N0/SB0/P0/B0/D2  J13500 
/N0/SB0/P0/B0/D3  J13600 


The size of logical bank 0 = 512MB = 4 DIMMS X 128MB (front of 256MB DIMM); 4 logical banks are interleaved together (4-way) to form Interleave Segment 0.


 


Example 2


     interleave-scope = within-board
     interleave-mode = optimal


Looking at SB4 we see one 4-way segment and two 2-way segments.


    

  • The 4-way segment (segment 2) is made up from P0/L0 P0/L2 P1/L0 P3/L0
    • 

  • The 1st 2-way segment (segment 3) is P1/L2 P3/L2
    • 

  • The 2nd 2-way segment (segment 4) is P2/L0 P2/L2
    • 



                     Logical  Logical  Logical 
               Port  Bank     Bank     Bank     DIMM    Interleave  Interleave
FRU Name        ID   Num      Size     Status   Size    Factor      Segment
-------------  ----  ----     ------   -------  ------  ----------  ----------
/N0/SB4/P0/B0   16    0      1024MB    pass      512MB     4-way       2
/N0/SB4/P0/B0   16    2      1024MB    pass      512MB     4-way       2
/N0/SB4/P1/B0   17    0      1024MB    pass      512MB     4-way       2
/N0/SB4/P1/B0   17    2      1024MB    pass      512MB     2-way       3
/N0/SB4/P2/B0   18    0       512MB    pass      256MB     2-way       4
/N0/SB4/P2/B0   18    2       512MB    pass      256MB     2-way       4
/N0/SB4/P3/B0   19    0      1024MB    pass      512MB     4-way       2
/N0/SB4/P3/B0   19    2      1024MB    pass      512MB     2-way       3



Example 3


     interleave-scope = within-cpu
     interleave-mode = optimal



Lets look at SB0/P0.


    

  • Below I disabled logical bank 0, to see what would happen.
    • 

  • Logical bank 3, which is the back of all the DIMMS in physical bank 1 forms interleave segment 1 (a 1-way interleave). It's all by itself.
    • 

  • Logical bank 1 (front of all the DIMMS in physical bank 1) and logical bank 2 ( back of all the DIMMS in physical bank 0 ) are interleaved together in segment 0
    • 



========================= Memory Configuration ===============================

                     Logical  Logical  Logical 
               Port  Bank     Bank     Bank     DIMM    Interleave  Interleave
FRU Name        ID   Num      Size     Status   Size    Factor      Segment
-------------  ----  ----     ------   -------  ------  ----------  ----------
/N0/SB0/P0/B1    0    1       512MB    pass      256MB     2-way       0
/N0/SB0/P0/B0    0    2       512MB    pass      256MB     2-way       0
/N0/SB0/P0/B1    0    3       512MB    pass      256MB     1-way       1

6800c-sc:A> showcomp sb0

Component           Status   Pending  POST   Description
---------           ------   -------  ----   -----------
/N0/SB0/P0          enabled  -        pass   UltraSPARC-III, 750MHz, 8M ECache
/N0/SB0/P1          enabled  -        pass   UltraSPARC-III, 750MHz, 8M ECache
/N0/SB0/P2          enabled  -        pass   UltraSPARC-III, 750MHz, 8M ECache
/N0/SB0/P3          enabled  -        pass   UltraSPARC-III, 750MHz, 8M ECache
/N0/SB0/P0/B0/L0    disabled -        untest 512M DRAM
/N0/SB0/P0/B0/L2    enabled  -        pass   512M DRAM
/N0/SB0/P0/B1/L1    enabled  -        pass   512M DRAM
/N0/SB0/P0/B1/L3    enabled  -        pass   512M DRAM





Example 4


     interleave-scope = across-boards
     interleave-mode = off


Below is an example with no interleaving . It's all 1-way.


========================= Memory Configuration ===============================

                     Logical  Logical  Logical 
               Port  Bank     Bank     Bank     DIMM    Interleave  Interleave
FRU Name        ID   Num      Size     Status   Size    Factor      Segment
-------------  ----  ----     ------   -------  ------  ----------  ----------
/N0/SB0/P0/B1    0    1       512MB    pass      256MB     1-way       0
/N0/SB0/P0/B0    0    2       512MB    pass      256MB     1-way       1
/N0/SB0/P0/B1    0    3       512MB    pass      256MB     1-way       2
/N0/SB0/P1/B0    1    0       512MB    pass      256MB     1-way       3
/N0/SB0/P1/B1    1    1       512MB    pass      256MB     1-way       4
/N0/SB0/P1/B0    1    2       512MB    pass      256MB     1-way       5
/N0/SB0/P1/B1    1    3       512MB    pass      256MB     1-way       6
/N0/SB0/P2/B0    2    0       512MB    pass      256MB     1-way       7
/N0/SB0/P2/B1    2    1       512MB    pass      256MB     1-way       8
/N0/SB0/P2/B0    2    2       512MB    pass      256MB     1-way       9
/N0/SB0/P2/B1    2    3       512MB    pass      256MB     1-way       10
/N0/SB0/P3/B0    3    0       512MB    pass      256MB     1-way       11
/N0/SB0/P3/B1    3    1       512MB    pass      256MB     1-way       12
/N0/SB0/P3/B0    3    2       512MB    pass      256MB     1-way       13
/N0/SB0/P3/B1    3    3       512MB    pass      256MB     1-way       14
/N0/SB3/P0/B0   12    0       512MB    pass      256MB     1-way       15
/N0/SB3/P0/B1   12    1       512MB    pass      256MB     1-way       16
/N0/SB3/P0/B0   12    2       512MB    pass      256MB     1-way       17
/N0/SB3/P0/B1   12    3       512MB    pass      256MB     1-way       18
/N0/SB3/P1/B0   13    0       512MB    pass      256MB     1-way       19
/N0/SB3/P1/B1   13    1       512MB    pass      256MB     1-way       20
/N0/SB3/P1/B0   13    2       512MB    pass      256MB     1-way       21
/N0/SB3/P1/B1   13    3       512MB    pass      256MB     1-way       22
/N0/SB3/P2/B0   14    0       512MB    pass      256MB     1-way       23
/N0/SB3/P2/B1   14    1       512MB    pass      256MB     1-way       24
/N0/SB3/P2/B0   14    2       512MB    pass      256MB     1-way       25
/N0/SB3/P2/B1   14    3       512MB    pass      256MB     1-way       26
/N0/SB3/P3/B0   15    0       512MB    pass      256MB     1-way       27
/N0/SB3/P3/B1   15    1       512MB    pass      256MB     1-way       28
/N0/SB3/P3/B0   15    2       512MB    pass      256MB     1-way       29
/N0/SB3/P3/B1   15    3       512MB    pass      256MB     1-way       30
/N0/SB4/P0/B0   16    0      1024MB    pass      512MB     1-way       31
/N0/SB4/P0/B0   16    2      1024MB    pass      512MB     1-way       32
/N0/SB4/P1/B0   17    0      1024MB    pass      512MB     1-way       33
/N0/SB4/P1/B0   17    2      1024MB    pass      512MB     1-way       34
/N0/SB4/P2/B0   18    0       512MB    pass      256MB     1-way       35
/N0/SB4/P2/B0   18    2       512MB    pass      256MB     1-way       36
/N0/SB4/P3/B0   19    0      1024MB    pass      512MB     1-way       37
/N0/SB4/P3/B0   19    2      1024MB    pass      512MB     1-way       38



 Example 5


     interleave-scope = within-board
     interleave-mode = optimal



    

  • 

    Notice below it has 2 16-way segments.
    

    • 

  • 

    And SB4 has 2 1-way segments.
    

      

    • 

      The reason it did not make a single 2-way segment on SB4 was 'optimal' only mixes DIMMS sizes when it can take small logical banks and form a logical bank that can then in turn be interleaved with a large logical bank. It's sort of like a 2 tier approach.
      

      • 

    

    • 



========================= Memory Configuration ===============================

                     Logical  Logical  Logical 
               Port  Bank     Bank     Bank     DIMM    Interleave  Interleave
FRU Name        ID   Num      Size     Status   Size    Factor      Segment
-------------  ----  ----     ------   -------  ------  ----------  ----------
/N0/SB0/P0/B0    0    0       512MB    pass      256MB    16-way       0
/N0/SB0/P0/B1    0    1       512MB    pass      256MB    16-way       0
/N0/SB0/P0/B0    0    2       512MB    pass      256MB    16-way       0
/N0/SB0/P0/B1    0    3       512MB    pass      256MB    16-way       0
/N0/SB0/P1/B0    1    0       512MB    pass      256MB    16-way       0
/N0/SB0/P1/B1    1    1       512MB    pass      256MB    16-way       0
/N0/SB0/P1/B0    1    2       512MB    pass      256MB    16-way       0
/N0/SB0/P1/B1    1    3       512MB    pass      256MB    16-way       0
/N0/SB0/P2/B0    2    0       512MB    pass      256MB    16-way       0
/N0/SB0/P2/B1    2    1       512MB    pass      256MB    16-way       0
/N0/SB0/P2/B0    2    2       512MB    pass      256MB    16-way       0
/N0/SB0/P2/B1    2    3       512MB    pass      256MB    16-way       0
/N0/SB0/P3/B0    3    0       512MB    pass      256MB    16-way       0
/N0/SB0/P3/B1    3    1       512MB    pass      256MB    16-way       0
/N0/SB0/P3/B0    3    2       512MB    pass      256MB    16-way       0
/N0/SB0/P3/B1    3    3       512MB    pass      256MB    16-way       0
/N0/SB3/P0/B0   12    0       512MB    pass      256MB    16-way       1
/N0/SB3/P0/B1   12    1       512MB    pass      256MB    16-way       1
/N0/SB3/P0/B0   12    2       512MB    pass      256MB    16-way       1
/N0/SB3/P0/B1   12    3       512MB    pass      256MB    16-way       1
/N0/SB3/P1/B0   13    0       512MB    pass      256MB    16-way       1
/N0/SB3/P1/B1   13    1       512MB    pass      256MB    16-way       1
/N0/SB3/P1/B0   13    2       512MB    pass      256MB    16-way       1
/N0/SB3/P1/B1   13    3       512MB    pass      256MB    16-way       1
/N0/SB3/P2/B0   14    0       512MB    pass      256MB    16-way       1
/N0/SB3/P2/B1   14    1       512MB    pass      256MB    16-way       1
/N0/SB3/P2/B0   14    2       512MB    pass      256MB    16-way       1
/N0/SB3/P2/B1   14    3       512MB    pass      256MB    16-way       1
/N0/SB3/P3/B0   15    0       512MB    pass      256MB    16-way       1
/N0/SB3/P3/B1   15    1       512MB    pass      256MB    16-way       1
/N0/SB3/P3/B0   15    2       512MB    pass      256MB    16-way       1
/N0/SB3/P3/B1   15    3       512MB    pass      256MB    16-way       1
/N0/SB4/P2/B0   18    0       512MB    pass      256MB     1-way       2
/N0/SB4/P3/B0   19    0      1024MB    pass      512MB     1-way       3


6800c-sc:A> showcomp sb4

Component           Status   Pending  POST   Description
---------           ------   -------  ----   -----------
/N0/SB4/P0          enabled  -        pass   UltraSPARC-III, 750MHz, 8M ECache
/N0/SB4/P1          enabled  -        pass   UltraSPARC-III, 750MHz, 8M ECache
/N0/SB4/P2          enabled  -        pass   UltraSPARC-III, 750MHz, 8M ECache
/N0/SB4/P3          enabled  -        pass   UltraSPARC-III, 750MHz, 8M ECache
/N0/SB4/P0/B0/L0    disabled -        untest 1024M DRAM
/N0/SB4/P0/B0/L2    disabled -        untest 1024M DRAM
/N0/SB4/P0/B1/L1    enabled  -        untest empty
/N0/SB4/P0/B1/L3    enabled  -        untest empty
/N0/SB4/P1/B0/L0    disabled -        untest 1024M DRAM
/N0/SB4/P1/B0/L2    disabled -        untest 1024M DRAM
/N0/SB4/P1/B1/L1    enabled  -        untest empty
/N0/SB4/P1/B1/L3    enabled  -        untest empty
/N0/SB4/P2/B0/L0    enabled  -        pass   512M DRAM
/N0/SB4/P2/B0/L2    disabled -        untest 512M DRAM
/N0/SB4/P2/B1/L1    enabled  -        untest empty
/N0/SB4/P2/B1/L3    enabled  -        untest empty
/N0/SB4/P3/B0/L0    enabled  -        pass   1024M DRAM
/N0/SB4/P3/B0/L2    disabled -        untest 1024M DRAM
/N0/SB4/P3/B1/L1    enabled  -        untest empty
/N0/SB4/P3/B1/L3    enabled  -        untest empty



 Example 6


     interleave-scope = within-board
     interleave-mode = fixed


For SB4 we have two 4-way segments and one 2-way segment.


    

  • 

    Notice that segment 0 and segment 2 contain different DIMM sizes.
    

    • 

  • 

    This is because we chose "fixed" and so different size DIMMs do not get interleaved together.
    

    • 



========================= Memory Configuration ===============================

                     Logical  Logical  Logical 
               Port  Bank     Bank     Bank     DIMM    Interleave  Interleave
FRU Name        ID   Num      Size     Status   Size    Factor      Segment
-------------  ----  ----     ------   -------  ------  ----------  ----------
/N0/SB4/P0/B0   16    0      1024MB    pass      512MB     4-way       0
/N0/SB4/P0/B0   16    2      1024MB    pass      512MB     4-way       0
/N0/SB4/P1/B0   17    0      1024MB    pass      512MB     4-way       0
/N0/SB4/P1/B0   17    2      1024MB    pass      512MB     2-way       1
/N0/SB4/P2/B0   18    0       512MB    pass      256MB     4-way       2
/N0/SB4/P2/B1   18    1       512MB    pass      256MB     4-way       2
/N0/SB4/P2/B0   18    2       512MB    pass      256MB     4-way       2
/N0/SB4/P2/B1   18    3       512MB    pass      256MB     4-way       2
/N0/SB4/P3/B0   19    0      1024MB    pass      512MB     4-way       0
/N0/SB4/P3/B0   19    2      1024MB    pass      512MB     2-way       1



 Example 7


     interleave-scope = within-board
     interleave-mode = optimal



This is a complicated interleave example, because "optimal" setting is mixing different DIMM sizes.


    

  • 

    It first interleaves smaller logical banks and then interleaves the resulting banks with other banks.
    

    • 

  • 

    It's only a single interleave segment, but lets see why we have these 8-way and 16-way parts.
    

      

    • 

      The 4 logical 512MB banks are first interleaved together to form 2 1024 logical banks. This is the first stage.
      

      • 

    • 

      So we now have 8 1024 logical banks to be interleaved together in the final stage.
      

      • 

    • 

      But since 2 of these 8 1024 banks are already 2-way interleaved segments they will end up being labeled as 16-way because 8 X 2-way = 16-way
      

      • 

    

    • 



 


========================= Memory Configuration ===============================

                     Logical  Logical  Logical 
               Port  Bank     Bank     Bank     DIMM    Interleave  Interleave
FRU Name        ID   Num      Size     Status   Size    Factor      Segment
-------------  ----  ----     ------   -------  ------  ----------  ----------
/N0/SB4/P0/B0   16    0      1024MB    pass      512MB     8-way       0
/N0/SB4/P0/B0   16    2      1024MB    pass      512MB     8-way       0
/N0/SB4/P1/B0   17    0      1024MB    pass      512MB     8-way       0
/N0/SB4/P1/B0   17    2      1024MB    pass      512MB     8-way       0
/N0/SB4/P2/B0   18    0       512MB    pass      256MB    16-way       0
/N0/SB4/P2/B1   18    1       512MB    pass      256MB    16-way       0
/N0/SB4/P2/B0   18    2       512MB    pass      256MB    16-way       0
/N0/SB4/P2/B1   18    3       512MB    pass      256MB    16-way       0
/N0/SB4/P3/B0   19    0      1024MB    pass      512MB     8-way       0
/N0/SB4/P3/B0   19    2      1024MB    pass      512MB     8-way       0



Component         J-No.   Size      Reason                                  
---------         -----   ----      ------                                  
SB0               -       -         No board power                 
         
SB1               -       -         No board power                          
SB2               -       -         No board power                          
SB3               -       -         No board power                          
/N0/SB4/P0/B0/D0  J13300  512 MB                                            
/N0/SB4/P0/B0/D1  J13400  512 MB                                            
/N0/SB4/P0/B0/D2  J13500  512 MB                                            
/N0/SB4/P0/B0/D3  J13600  512 MB                                            
/N0/SB4/P0/B1     -       -         DRAM DIMM Group 1 Empty                 
/N0/SB4/P1/B0/D0  J14300  512 MB                                            
/N0/SB4/P1/B0/D1  J14400  512 MB                                            
/N0/SB4/P1/B0/D2  J14500  512 MB                                            
/N0/SB4/P1/B0/D3  J14600  512 MB                                            
/N0/SB4/P1/B1     -       -         DRAM DIMM Group 1 Empty                 
/N0/SB4/P2/B0/D0  J15300  256 MB                                            
/N0/SB4/P2/B0/D1  J15400  256 MB                                            
/N0/SB4/P2/B0/D2  J15500  256 MB                                            
/N0/SB4/P2/B0/D3  J15600  256 MB                                            
/N0/SB4/P2/B1/D0  J15301  256 MB                                            
/N0/SB4/P2/B1/D1  J15401  256 MB                                            
/N0/SB4/P2/B1/D2  J15501  256 MB                                            
/N0/SB4/P2/B1/D3  J15601  256 MB                                            
/N0/SB4/P3/B0/D0  J16300  512 MB                                            
/N0/SB4/P3/B0/D1  J16400  512 MB                                            
/N0/SB4/P3/B0/D2  J16500  512 MB                                            
/N0/SB4/P3/B0/D3  J16600  512 MB                                            
/N0/SB4/P3/B1     -       -         DRAM DIMM Group 1 Empty


6800c-sc:A> showcomp sb4

Component           Status   Pending  POST   Description
---------           ------   -------  ----   -----------
/N0/SB4/P0          enabled  -        pass   UltraSPARC-III, 750MHz, 8M ECache
/N0/SB4/P1          enabled  -        pass   UltraSPARC-III, 750MHz, 8M ECache
/N0/SB4/P2          enabled  -        pass   UltraSPARC-III, 750MHz, 8M ECache
/N0/SB4/P3          enabled  -        pass   UltraSPARC-III, 750MHz, 8M ECache
/N0/SB4/P0/B0/L0    enabled  -        pass   1024M DRAM
/N0/SB4/P0/B0/L2    enabled  -        pass   1024M DRAM
/N0/SB4/P0/B1/L1    enabled  -        untest empty
/N0/SB4/P0/B1/L3    enabled  -        untest empty
/N0/SB4/P1/B0/L0    enabled  -        pass   1024M DRAM
/N0/SB4/P1/B0/L2    enabled  -        pass   1024M DRAM
/N0/SB4/P1/B1/L1    enabled  -        untest empty
/N0/SB4/P1/B1/L3    enabled  -        untest empty
/N0/SB4/P2/B0/L0    enabled  -        pass   512M DRAM
/N0/SB4/P2/B0/L2    enabled  -        pass   512M DRAM
/N0/SB4/P2/B1/L1    enabled  -        pass   512M DRAM
/N0/SB4/P2/B1/L3    enabled  -        pass   512M DRAM
/N0/SB4/P3/B0/L0    enabled  -        pass   1024M DRAM
/N0/SB4/P3/B0/L2    enabled  -        pass   1024M DRAM
/N0/SB4/P3/B1/L1    enabled  -        untest empty
/N0/SB4/P3/B1/L3    enabled  -        untest empty


 


The following doc can be used to understand DIMM sizes:


DIMM Size Reference Sheet for Sun Fire Midrange and Highend Servers (Doc ID 1325039.1)


 


To discuss this information further with Oracle experts and industry peers, we encourage you to review, join or start a discussion in an appropriate 
My Oracle Support Community - Oracle Sun Technologies Community.



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