Sun Ultra[TM] 45 Workstation: POST Levels

Asset ID:	1-71-1005245.1
Update Date:	2017-02-01
Keywords:

Solution Type Technical Instruction Sure

Solution 1005245.1 : Sun Ultra[TM] 45 Workstation: POST Levels

Applies to:

Sun Ultra 45 Workstation - Version Not Applicable and later
All Platforms

Goal

POST tests executed in Min and Max mode on Sun Ultra[TM] 45 (codename "Chicago") Workstations.

Fix

Steps to Follow

This brief document lists out the different POST tests executed by POST in
min and max modes.
This has been specifically tailored for Sun Ultra[TM] 45, though it may hold true for other platforms as well.
When "diag_level = min"
-----------------------
1. Master CPU Init Critical Resources
-SRAM globals
-UART
-Set Watchdog Timeout
2. Master CPU Test
-Internal Regs Test
-IMMU
-DMMU
-L2 cache (stack region)
-Stick and Tick register tests
-Interrupts
3. Slave CPU Test
-Internal Regs Test
-IMMU
-DMMU
-L2 cache (stack region)
-Stick and Tick Register tests
-Interrupts
4. Master CPU I2C
-Init I2C Controllers
-Probe Board Fruprom
-Probe DDR Memory Fruproms
-Print Board Serial and Part info
5. Master CPU Memory
-Initialize Memory Controller
-Test DDRAM DIMM Interconnect
-Move POST to Master CPU Memory
6. Slave CPU Memory
-Initialize Memory Controller
-Master CPU test Slave CPU s Memory
-Test JBUS Interconnect to Slave CPU Modules
-Test Slave CPU DDRAM Interconnect
8.Slave CPU Executes POST from Master Memory
9.All CPUs Test Floating Point Unit 1
10. All CPUs Scrub and Enable all Internal Caches
-Icache
-Dcache
-Pcache
-Wcache
11.All CPUs Scrub their Memory
12.All CPUS do quick Block Memory test
13.Master CPU Tests X-Bus SRAM
14.Master CPU Tests IO-Bridge(s)
- IO-Bridge JBUS quick check
- IO-Bridge Quick Read Initialization Test
- IO-Bridge Init test
- IO-Bridge Register test
- IO-bridge Interrupt test
- PCI config read test (device ID and vendor ID)
When "diag_level = max"
-----------------------
Includes all test suite performed when diag_level is set to min plus
the follwoing tests:
1.All CPUs run L2$ Tag Test (part of Step 2 and 3 of Min Mode)
2.Master CPU prints the DIMM Serial and Part information (Part of step 4 of Min Mode )
3.All CPUs do Functional Internal Caches Tests (Part of step 10 of Min Mode)
-Icache
-Dcache
-Pcache
-Wcache
-L2-cache
4. All CPUS do full suite of Functional Tests on these blocks
-IMMU
-DMMU
-FPU
-Graphics
-Unit
-ECC error test
5. All CPUs do Full Memory Test
Block Memory (DDRAM internal cell integrity test) instead of quick Block Memory test.

Product
Sun Ultra 45 Workstation

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