Fujitsu SPARC M12-2S
 
Fujitsu SPARC M12-2
 

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In this Document

Purpose

Details

References

Applies to:

Purpose

Provide additional information for message ID: M12-if.ce-cpu-cpu

Fujitsu fault codes:

15024100, 15024101, 15024102, 15024103, 15024200, 15024201,
15024202, 15024203,

Details

Type

Hardware Fault

   if.ce-cpu-cpu

Severity

Major

Description

Fault due to persistent correctable errors on the interface between two CPU chips.

When the number of correctable error exceeds a predetermined threshold the lane is degraded and operates at a reduced bandwidth.

Automated Response

No immediate action will be taken.

Impact

The CPU chip is deconfigured.

Indicted Hardware

For M12-2/M12-S systems, the CMUU or CMUL where this CPU chip is mounted is marked for replacement.

When the fault is detected between a CPU chip on CMUL and a CPU chip on CMUU, there is a chance that the BPU between CMUL and CMUU has a problem.

For M12-2/M12-2S system with 2 CPU chips in a box, configuration of PCIe fabric will be changed triggered by CPU chip deconfiguration. This takes place when ioreconfigure is set to true by the setpparmode command.

Configuration of the PCIe fabric is changed to maintain access to all the onboard devices and PCIe slots when either CMUU or CMUL is deconfigured.

Suggested Action for System Administrator

The recommended service action for this event is to schedule replacement of the affected component(s) at the earliest possible convenience. Although the hardware may be functioning, it is not intended nor recommended that the faulted component(s) remain in the system for a prolonged period of time.

Refer to the following document for the latest procedures for displaying event content in preparation for submitting a service request and applying any post-repair actions that may be required.

PSH Procedural Article for Fujitsu M10 Diagnosis (Doc ID 1525156.1)

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