SPARC M7-8
 
SPARC M8-8
 
SPARC M7-16
 

PLA-Support>Sun Systems>SPARC>Enterprise>SN-SPARC: M7
 

In this Document

Purpose

Scope

Details

References

Applies to:

Purpose

Solaris[TM] device paths and messaging reference the ID of a given processor (in /var/adm/messages, console logs, core files, OBP probing, FMA logs etc.).

By correctly mapping this ID to a physical location, we know that we are servicing the right component to resolve a hardware problem. An incorrect mapping could result in replacing and/or servicing the wrong component and could cause further outages or problems on the platform.
Also, on a sun4v architecture such as the M7 platforms, this may help to understand how the cpus are assigned to the various domains.

When FMA indicts an component, the decoding is obviously automatically done and the indicted CMP or CMIOU is the one to be serviced.

Scope

This documents provides information about SPARC M8 and SPARC M7 servers CPU decoding.

References : SPARC M8 and SPARC M7 Servers Administration Guide http://docs.oracle.com/cd/E55211_01/

Details

A SPARC M7 processor is composed of 32 fourth generation CMT cores (S4).  Each S4 core is Dynamically Threaded, 1 to 8 Threads Per Core.
A SPARC M8 processor is composed of 32 fifth generation CMT cores (S5). Each S5 core is Dynamically Threaded, 1 to 8 Threads Per Core.
Solaris often uses the equivalent terminology strand in place of the term thread.

A CPU, memory, and I/O unit (CMIOU) is equipped with either one SPARC M7 processor or one SPARC M8 processor.
Consequently, a CMIOU has 32 cores, 256 threads.

A SPARC M7-8 or M8-8 server with one Pdomain supports one physical domain, up to eight CMIOUs.
The single physical domain can have up to eight processors, 256 cores, 2048 threads.

A SPARC M7-8 or M8-8 server with two Pdomains supports two physical domains, up to four CMIOUs per physical domain.
Each of the two physical domains can have up to four processors, 128 cores, 1024 threads.

A SPARC M7-16 is composed of Domain Configuration Unit (DCU).
An M7-16 physical domain can be assigned one to four DCUs.
A DCU is composed of two to four CMIOUs.
So an M7-16 server is composed of up to 16 M7 processors, 128 cores, 4096 threads.


ILOM :

From an ILOM perspective, each CMIOU (CMIOU[0-15]) has 1 CPU Module (CM) and one Host Processor (CMP).
The NAC format for the SPARC M7 as visible from the ILOM shell is:

• /System/Processors/CPUs/CPU_[0-15]
• /SYS/CMIOU[0-15]/CM/CMP

Example

For SPARC M7-8 and M8-8 servers with one Pdomain , DCU0 is composed of the following CMIOU/CMP :

DCU    NAC Name                            ipmi_name    SDM
DCU0  /SYS/CMIOU[0-7]/CM/CMP    /CPU[0-7]      /System/Processors/CPUs/CPU_[0-7]

For SPARC M7-8and M8-8 servers with 2 Pdomains , each DCU (DCU[0-1]) is composed of the following CMIOU/CMP :

DCU      NAC Name                            ipmi_name    SDM
DCU0    /SYS/CMIOU[0-3]/CM/CMP    /CPU[0-3]     /System/Processors/CPUs/CPU_[0-3]
DCU1    /SYS/CMIOU[4-7]/CM/CMP    /CPU[4-7]     /System/Processors/CPUs/CPU_[4-7]

For SPARC M7-16 servers , each DCU (DCU[0-3]) is composed of the following CMIOU/CMP :

DCU      NAC Name                                ipmi_name    SDM
DCU0    /SYS/CMIOU[0-3]/CM/CMP        /CPU[0-3]      /System/Processors/CPUs/CPU_[0-3]
DCU1    /SYS/CMIOU[4-7]/CM/CMP        /CPU[4-7]      /System/Processors/CPUs/CPU_[4-7]
DCU2    /SYS/CMIOU[8-11]/CM/CMP      /CPU[8-11]    /System/Processors/CPUs/CPU_[8-11]
DCU3    /SYS/CMIOU[12-15]/CM/CMP    /CPU[12-15]   /System/Processors/CPUs/CPU_[12-15]


You can obtain a summary of the chassis configuration as following :

For each Pdomain

Each CMP is composed with 8 SPARC Cores Clusters (SCC).

Each SCC is composed of 4 cores.

Each core is composed of 8 threads.

From ILOM :

• /SYS/CMIOU[0-15]/CM/CMP/SCC[0-7]/CORE[0-3]/P[0-7]

The OBP and Solaris commands below will report the core and thread IDs.

OBP Device tree :

As soon as the Host has been started and OBP is running, the CPUIDs are visible in hexadecimal format as following :

Solaris :

From Solaris, the following commands are available from Control and Guest domains in order to identify and locate CPUs :

• psrinfo
• prtdiag
• prtpicl
• fmtopo

When cpus are assigned to guest domains, the allocation can be checked using the ldm command from the control domain.
Otherwise, check the cupid from the guest domain itself.

The fmtopo output provides provides good mix for both logical and physical information.

From the prtpicl output

From the psrinfo output, in the following example, we can determined which strands are missing :

The easiest way to determine the physical location and allocation of CPU resources is to use the below ldm commands introduced in OVM 3.2. Run the below command in the control domain.  The complete list of core ids and CPU sets is listed in this file attachment - cmu-cid-cpuset as additional reference.

Example of an M7-8 host :

References

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