Fujitsu M10-4
 
Fujitsu M10-1
 
Fujitsu M10-4S
 

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In this Document

Purpose

Details

References

Applies to:

Purpose

Provide additional information for message ID: M10-i2c.device-internal

Fujitsu fault codes:

01920102, 01920103, 01920104

Details

Type

Hardware Fault

   i2c.device-internal

Severity

Major

Description

Fault due to an I2C access failure to a specific chip, where the data read back from the chip does not match the data that was written to the chip.

This type of fault implies that the chip may be configured incorrectly, and the consequences of the fault are quite unpredictable.

Examples of chips that are affected by this fault and the types of consequences that might occur:

- CPU chips on Motherboards: The PPAR using this CPU chip may reset or may hang or some other problem may occur;
- XB chips on XBU: The PPARs using this XB chip may reset or may hang or some other problem may occur.
- IOC logic on CPU chips: hardware may be degraded but PPAR functionality is not impaired i.e. Solaris sees a full complement of functional cpus.

Automated Response

No immediate action is taken. The platform administrator should schedule a service action.

Impact

If the chip being accessed is a CPU chip: The CPU chip may be deconfigured when the PPAR using the CPU chip reboots. If the IOC logic on a CPU chip is being accessed, cpus may be marked as Degraded by XSCF but be functional and configured into the PPAR as part of the Solaris configuration.

When the chip being accessed is a PCI express switch chip, this chip is deconfigured.

Indicted Hardware

If the chip being accessed is a CPU chip:

For M10-1 systems, the MBU is marked for replacement.

For M10-4 or M10-4S systems, the CMUU or CMUL where the faulty CPU chip is mounted, is marked for replacement.

For M10-4/4S system with 4 CPU chip in a box, configuration of PCIe fabric will be changed triggered by CPU chip deconfiguration. This is taken place when ioreconfigure is set to true by setpparmode command.

Configuration of PCIe fabric is changed as follows:

- When CPU#0 on CMUL is deconfigured: Configuration of PCIe switch 0 is changed to allow access from CPU#0 on CMUU to built-in SAS chip, USB chip and GbE i/f #0 and #1. Configuration of PCIe switch 1 is changed to allow access from CPU#0 on CMUU to the first PCIe slot.

- When CPU#1 on CMUL is deconfigured: Configuration of PCIe switch 2 is changed to allow access from CPU#1 on CMUU to the fourth and fifth PCIe slots. Configuration of PCIe switch 3 is changed to allow access from CPU#1 on CMUU to the eighth and ninth PCIe slot.

- When CPU#0 on CMUU is deconfigured: Configuration of PCIe switch 0 is changed to allow access from CPU#0 on CMUL to built-in GbE i/f #2 and #3. Configuration of PCIe switch 1 is changed to allow access from CPU#0 on CMUL to the second and third PCIe slots.

- When CPU#1 on CMUU is deconfigured: Configuration of PCIe switch 2 is changed to allow access from CPU#1 on CMUL to the sixth and seventh PCIe slots. Configuration of PCIe switch 3 is changed to allow access from CPU#1 on CMUL to the tenth and eleventh PCIe slot.

If the chip being accessed is a XB chip: A XB way of PPARs, which are using this XB chip, is deconfigured.

If the logic area of the CPU chip(s) being accessed is the IOC, both cpus may be marked as degraded but still function within the PPAR configuration i.e. Solaris sees a full complement of functional cpus but XSCF will report the cpus as Degraded:

XSCF> showstatus
BB#00 Status:Normal;
* CMUU Status:Degraded;
* CPU#0 Status:Degraded;
* CPU#1 Status:Degraded;

Suggested Action for System Administrator

The recommended service action for this event is to schedule replacement of the affected component(s) at the earliest possible convenience. Although the hardware may be functioning, it is not intended nor recommended that the faulted component(s) remain in the system for a prolonged period of time.

Refer to the following document for the latest procedures for displaying event content in preparation for submitting a service request and applying any post-repair actions that may be required.

PSH Procedural Article for Fujitsu M10 Diagnosis (Doc ID 1525156.1)

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