Fujitsu M10-4
 
Fujitsu M10-1
 
Fujitsu M10-4S
 

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In this Document

Purpose

Details

References

Applies to:

Purpose

Provide additional information for message ID: M10-i2c.device_cmu

Fujitsu fault codes:

01920202, 01920205

Details

Type

Hardware Fault

   i2c.device_cmu

Severity

Major

Description

Fault due to a I2C write failure to a specific chip.

The I2C write operation is performed when configuring the chips. I2C is used to access CPU chips or PCI express switch chips on MBU(for M10-1 servers) or CMUL(for M10-4/4S servers).

Automated Response

If this fault takes place while the platform is powering up or while a FRU is powering up, then the FRU with the chip will not be configured into the system.

Otherwise, no immediate action is taken. The platform administrator should schedule a service action.

Impact

If the chip being accessed is a CPU chip:

The CPU chip is deconfigured when the PPAR using the CPU chip reboots.

When the chip being accessed is a PCI express switch chip, this chip is deconfigured.

Indicted Hardware

If the chip being accessed is a CPU chip:

For M10-1 systems, the MBU is marked for replacement.

For M10-4/4S systems: the CMUU or CMUL, where the suspicious CPU chip is mounted, is marked for replacement. If the first suspect is CMUU, there is a small chance that MBC on CMUL is faulty.

If the chip being accessed is a PCI express switch chip:

For M10-1 servers, MBU is marked for replacement.
For M10-4/4S servers, CMUL is marked for replacement.

For M10-4/4S system with 4 CPU chip in a box, configuration of PCIe fabric will be changed triggered by CPU chip deconfiguration. This is taken place when ioreconfigure is set to true by setpparmode command.

Configuration of PCIe fabric is changed as follows:

- When CPU#0 on CMUL is deconfigured: Configuration of PCIe switch 0 is changed to allow access from CPU#0 on CMUU to built-in SAS chip, USB chip and GbE i/f #0 and #1. Configuration of PCIe switch 1 is changed to allow access from CPU#0 on CMUU to the first PCIe slot.

- When CPU#1 on CMUL is deconfigured: Configuration of PCIe switch 2 is changed to allow access from CPU#1 on CMUU to the fourth and fifth PCIe slots. Configuration of PCIe switch 3 is changed to allow access from CPU#1 on CMUU to the eighth and ninth PCIe slot.

- When CPU#0 on CMUU is deconfigured: Configuration of PCIe switch 0 is changed to allow access from CPU#0 on CMUL to built-in GbE i/f #2 and #3. Configuration of PCIe switch 1 is changed to allow access from CPU#0 on CMUL to the second and third PCIe slots.

- When CPU#1 on CMUU is deconfigured: Configuration of PCIe switch 2 is changed to allow access from CPU#1 on CMUL to the sixth and seventh PCIe slots. Configuration of PCIe switch 3 is changed to allow access from CPU#1 on CMUL to the tenth and eleventh PCIe slot.

Suggested Action for System Administrator

The recommended service action for this event is to schedule replacement of the affected component(s) at the earliest possible convenience. Although the hardware may be functioning, it is not intended nor recommended that the faulted component(s) remain in the system for a prolonged period of time.

Refer to the following document for the latest procedures for displaying event content in preparation for submitting a service request and applying any post-repair actions that may be required.

PSH Procedural Article for Fujitsu M10 Diagnosis (Doc ID 1525156.1)

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