Fujitsu M10-4S
 

PLA-Support>Sun Systems>Sun_Other>Sun Collections>SN-OTH: Sun PSH
 

In this Document

Purpose

Details

References

Applies to:

Purpose

Provide additional information for message ID: M10-if.ce-xb-cpu

Fujitsu fault codes:

0506000d, 0506000e, 0506000f, 05060010, 0506010f, 05060110, 05060111,
05060112, 05060113, 05060114, 05060115, 05060116, 05060208, 05060209,
0506020a, 0506020b

Details

Type

Hardware Fault

   if.ce-xb-cpu

Severity

Major

Description

Fault due to a permanent correctable error on the interface between a CPU chip on a CMUU or a CMUL and a XB-chip on an XBUQ.

When the number of correctable error exceeds a predetermined threshold the lane is degraded and operates at a reduced speed.

Automated Response

No immediate action will be taken.

Impact

A CPU is deconfigured.

Indicted Hardware

The XBUQ is the first suspect and CMUU or CMUL is the second suspect.

For M10-4/4S system with 4 CPU chip in a box, configuration of PCIe fabric will be changed triggered by CPU chip deconfiguration. This is taken place when ioreconfigure is set to true by setpparmode command.

Configuration of PCIe fabric is changed as follows:

- When CPU#0 on CMUL is deconfigured:

Configuration of PCIe switch 0 is changed to allow access from CPU#0 on CMUU to built-in SAS chip, USB chip and GbE i/f #0 and #1.

Configuration of PCIe switch 1 is changed to allow access from CPU#0 on CMUU to the first PCIe slot.

- When CPU#1 on CMUL is deconfigured:

Configuration of PCIe switch 2 is changed to allow access from CPU#1 on CMUU to the fourth and fifth PCIe slots.
Configuration of PCIe switch 3 is changed to allow access from CPU#1 on CMUU to the eighth and ninth PCIe slot.

- When CPU#0 on CMUU is deconfigured:

Configuration of PCIe switch 0 is changed to allow access from CPU#0 on CMUL to built-in GbE i/f #2 and #3.
Configuration of PCIe switch 1 is changed to allow access from CPU#0 on CMUL to the second and third PCIe slots.

- When CPU#1 on CMUU is deconfigured:

Configuration of PCIe switch 2 is changed to allow access from CPU#1 on CMUL to the sixth and seventh PCIe slots.
Configuration of PCIe switch 3 is changed to allow access from CPU#1 on CMUL to the tenth and eleventh PCIe slot.

Suggested Action for System Administrator

The recommended service action for this event is to schedule replacement of the affected component(s) at the earliest possible convenience. Although the hardware may be functioning, it is not intended nor recommended that the faulted component(s) remain in the system for a prolonged period of time.

Refer to the following document for the latest procedures for displaying event content in preparation for submitting a service request and applying any post-repair actions that may be required.

PSH Procedural Article for Fujitsu M10 Diagnosis (Doc ID 1525156.1)

This solution has no attachment