Fujitsu M10-4
 
Fujitsu M10-1
 
Fujitsu M10-4S
 

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In this Document

Purpose

Details

References

Applies to:

Purpose

Provide additional information for message ID: M10-ioc.ch.fe

Fujitsu fault codes:

02002400, 02002421, 02002423, 02002424, 02002425, 02002426,
02002427, 02002428, 02002429, 0200242a, 0200242b, 02002432

Details

Type

Hardware Fault

   ioc.ch.fe

Severity

Major

Description

Fault due to a fatal error within an IOC, which is related to an IO Channel.

Automated Response

The domain using the IO Channel (IOC) is reset.

Impact

The IOC (root complex in a CPU chip) is deconfigured.

Indicted Hardware

For M10-1 systems, the MBU is marked for replacement.

For M10-4/4S systems, the CMUU or CMUL, where a CPU chip contains affected IOC, is marked for replacement.

If the fault was detected while running POST, such event is listed in the following categories:

- fe-reg-cmp-err 02002400, 02002421, 02002423, 02002424, 02002425, 02002432 The expected result is not obtained by reading an IO
  channel register
- fe-dma-test-err 02002426, 02002427 DMA test faced uncorrectable error
- fe-msi-test-err 02002428, 02002429, 0200242a, 0200242b MSI test face unrecoverable error

For M10-4/4S system with 4 CPU chip in a box, configuration of PCIe fabric will be changed triggered by IOC deconfiguration. This is taken place when ioreconfigure is set to true by setpparmode command.

Configuration of PCIe fabric is changed as follows:

- When IOC#0 in CPU#0 on CMUL is deconfigured: Configuration of PCIe switch 0 is changed to allow access from CPU#0
  on CMUU to built-in SAS chip, USB chip and GbE i/f #0 and #1.
- When IOC#1 in CPU#0 on CMUL is deconfigured: Configuration of PCIe switch 1 is changed to allow access from CPU#0
  on CMUU to the first PCIe slot.
- When IOC#0 in CPU#1 on CMUL is deconfigured: Configuration of PCIe switch 2 is changed to allow access from CPU#1
  on CMUU to the fourth and fifth PCIe slots.
- When IOC#1 in CPU#1 on CMUL is deconfigured: Configuration of PCIe switch 3 is changed to allow access from CPU#1

  on CMUU to the eighth and ninth PCIe slot.
- When IOC#0 in CPU#0 on CMUU is deconfigured: Configuration of PCIe switch 0 is changed to allow access from CPU#0
  on CMUL to built-in GbE i/f #2 and #3.
- When IOC#1 in CPU#0 on CMUU is deconfigured: Configuration of PCIe switch 1 is changed to allow access from CPU#0
  on CMUL to the second and third PCIe slots.
- When IOC#0 in CPU#1 on CMUU is deconfigured: Configuration of PCIe switch 2 is changed to allow access from CPU#1
  on CMUL to the sixth and seventh PCIe slots.
- When IOC#1 in CPU#1 on CMUU is deconfigured: Configuration of PCIe switch 3 is changed to allow access from CPU#1
  on CMUL to the tenth and eleventh PCIe slot.

Suggested Action for System Administrator

The recommended service action for this event is to schedule replacement of the affected component(s) at the earliest possible convenience. Although the hardware may be functioning, it is not intended nor recommended that the faulted component(s) remain in the system for a prolonged period of time.

Refer to the following document for the latest procedures for displaying event content in preparation for submitting a service request and applying any post-repair actions that may be required.

PSH Procedural Article for Fujitsu M10 Diagnosis (Doc ID 1525156.1)

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