M10-cpu.se-offlinereq - Too many CPU faults, such as 05012100, have occurred

Solution Type Predictive Self-Healing Sure

Solution 1526350.1 : M10-cpu.se-offlinereq - Too many CPU faults, such as 05012100, have occurred

Applies to:

Fujitsu M10-4S
Fujitsu M10-1
Fujitsu M10-4
SPARC

Provide additional information for message ID: M10-cpu.se-offlinereq

Fujitsu fault codes:

05012400, 05012401, 05012403, 05012404

Type

Severity

Description

: Fault that indicates too many CPU serious faults, such as 05012100, have occurred.

Automated Response

: No immediate action is taken. The affected CPU may take a UE trap, enter RED state or encounter a data UE. If the domain does not panic the administrator should ensure that the affected CPU is removed from the domain configuration. Additionally, all future CPU serious fault interrupts are blocked.

Impact

: The CPU chip is deconfigured the next time the domain reboots. For M10-1 systems, this means the platform becomes unbootable.

Indicted Hardware

: For M10-1 systems the Motherboard is marked for replacement. For M10-4 and M10-4S systems, the related Motherboard (CMUU or CMUL) is marked for replacement.; For M10-4/4S system with 4 CPU chip in a box, configuration of PCIe fabric will be changed triggered by CPU chip deconfiguration. This is taken place when ioreconfigure is set to true by setpparmode command.; Configuration of PCIe fabric is changed as follows:; - When CPU#0 on CMUL is deconfigured: Configuration of PCIe switch 0 is changed to allow access from CPU#0 on CMUU to built-in SAS chip, USB chip and GbE i/f #0 and #1. Configuration of PCIe switch 1 is changed to allow access from CPU#0 on CMUU to the first PCIe slot.; - When CPU#1 on CMUL is deconfigured: Configuration of PCIe switch 2 is changed to allow access from CPU#1 on CMUU to the fourth and fifth PCIe slots. Configuration of PCIe switch 3 is changed to allow access from CPU#1 on CMUU to the eighth and ninth PCIe slot.; - When CPU#0 on CMUU is deconfigured: Configuration of PCIe switch 0 is changed to allow access from CPU#0 on CMUL to built-in GbE i/f #2 and #3. Configuration of PCIe switch 1 is changed to allow access from CPU#0 on CMUL to the second and third PCIe slots.; - When CPU#1 on CMUU is deconfigured: Configuration of PCIe switch 2 is changed to allow access from CPU#1 on CMUL to the sixth and seventh PCIe slots. Configuration of PCIe switch 3 is changed to allow access from CPU#1 on CMUL to the tenth and eleventh PCIe slot.

Suggested Action for System Administrator

: The recommended service action for this event is to schedule replacement of the affected component(s) at the earliest possible convenience. Although the hardware may be functioning, it is not intended nor recommended that the faulted component(s) remain in the system for a prolonged period of time.

Refer to the following document for the latest procedures for displaying event content in preparation for submitting a service request and applying any post-repair actions that may be required.

PSH Procedural Article for Fujitsu M10 Diagnosis (Doc ID 1525156.1)

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