![]() | Oracle System Handbook - ISO 7.0 May 2018 Internal/Partner Edition | ||
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Solution Type Sun Alert Sure Solution 2027245.1 : SPARC T5 Series and SPARC M5-32/M6-32 Servers System Firmware Version 9.4.2.c and 9.4.2.d May Erroneously Disable CPUs
In this Document
Applies to:SPARC T5-8SPARC T5-1B Netra SPARC T5-1B Server Module SPARC M5-32 SPARC M6-32 SPARC SPARC M5-32 SPARC M6-32 ______________________________________ Date of Preliminary Release: 02-Jul-2015 Date of Resolved Release: 13-Jul-2015 ______________________________________ DescriptionFor SPARC T5 Series and SPARC M5-32/M6-32 Servers system firmware, the memory retirement function supports the ability to take portions of memory DIMMs offline proactively in response to certain error conditions. With system firmware Version 9.4.2.c and 9.4.2.d, when a retirement occurs, and during subsequent boots, the firmware will also disable the perfectly functional CPUs with which that memory is associated. This can result in a loss of performance or the inability to bind resources to guest domains. Note: Firmware 9.4.2.c and 9.4.2.d have been WITHDRAWN and are no longer available for download. OccurrenceThis issue can occur on the following platforms:
Note: No other systems or platforms are affected by this issue. To determine the firmware version installed on the system, use the following ILOM command: SymptomsShould the described issue occur, the system will report missing CPUs. This can present itself as a loss of performance, the inability to bind resources to guest domains, and most obviously, when the affected system is rebooted, the host console will show messages similar to the following: WorkaroundThere is no workaround for this issue. This issue is addressed in the following releases:
History02-Jul-2015: Document released, status Preliminary This regression was caused by the change for bug 20656570. References<BUG:21299503> - REBOOT OF HOST DECONFIGURES HARDWARE WITH INVALID HV ERRORSAttachments This solution has no attachment |
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