Information in this document applies to any platform.
Date of Resolved Release: 30-Jan-2014
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Description
Use of firmware 9.0.1__ ( where __ = an alphabetical letter) on SPARC M6-32 systems and SPARC M5-32 systems with M6 CPU/Memory Unit (CMU) is not recommended due to the possibility of a Solaris panic. Exposure may occur on systems with a faulty DIMM when the M6 pin sparing circuit is utilized.
Occurrence
This issue can occur on the following platforms:
- SPARC M6-32 Servers with Firmware version 9.0.1__
- SPARC M5-32 Servers (with M6 CMUs installed) with Firmware version 9.0.1__
Notes:
1. No other platforms or M-series servers are affected by this issue.
2. This issue can only occur on the M6-32 or M5-32 (with M6 CMUs installed) where a faulty DIMM is present.
To determine the current firmware version on one of these servers, do the following:
-> show /HOST0 sysfw_version
/HOST0
Properties:
sysfw_version = Sun System Firmware 9.0.1i
Symptoms
Occurrence of this issue can lead to a system panic.
Workaround
There is no workaround for this issue.
This issue is addressed in the following release:
- Sun System Firmware version 9.1.1a (as delivered in patch 17944131 or later)
For the latest information on Firmware upgrade for these systems, see:
"SPARC M5-32 and M6-32 Servers: Firmware Image Software Version Matrix Information" <Document:1540816.1>
and:
"Information Center: SPARC M5-32 and SPARC M6-32 Servers" <Document:1558958.2>
NOTE: It is STRONGLY recommended to upgrade the M5-32/M6-32 server firmware to version 9.1.1a at the earliest opportunity.
Firmware 9.1.1a is considered the minimum operating firmware for M6-32 servers and M5-32 servers with M6 CMU board(s).
Patches
<SUNPATCH:17944131>
History
30-Jan-2014: Document released; status is Resolved
06-Feb-2014: Maintenance update/edit; no change in content
This issue was introduced with the implementation of CR17861184.
The exposure only happens when a bad memory chip is present on the server,
and the M6's pin sparing circuit is utilized.
If a pin spare occurs and the bad chip register is left
incorrectly programmed, then a subsequent multi-bit error
in a DIMM associated with this incorrect programming would
result in a UE rather than being correctable.
Internal Contributor/Submitter: Bill.Blohm@Oracle.Com
Internal Eng Responsible Engineer: barbara.burkhardt@oracle.com
Oracle Knowledge Analyst: david.mariotto@oracle.com
Internal Eng Business Unit Group: SPARC Systems
Internal Associated SRs:
Internal Resolution Patches: 17944131
References
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