Non-zero ERRCNT and LNERR values could be seen during POST on either SPARC T4-1. SPARC T4-2, or SPARC T4-4 servers

Asset ID:	1-72-1612921.1
Update Date:	2017-10-05
Keywords:

Solution Type Problem Resolution Sure

Solution 1612921.1 : Non-zero ERRCNT and LNERR values could be seen during POST on either SPARC T4-1. SPARC T4-2, or SPARC T4-4 servers

Applies to:

SPARC T4-1 - Version All Versions to All Versions [Release All Releases]
SPARC T4-2 - Version All Versions to All Versions [Release All Releases]
SPARC T4-4 - Version All Versions to All Versions [Release All Releases]
Information in this document applies to any platform.
The messages have this format:

[CPU 0:0:0] NOTICE: SMI Channel 0, SB Mapping 0 -- ERRCNT: 0x0 LNERR: 0x0
[CPU 0:0:0] NOTICE: SMI Channel 0, SB Mapping 1 -- ERRCNT: 0x0 LNERR: 0x0
[CPU 0:0:0] NOTICE: SMI Channel 1, SB Mapping 0 -- ERRCNT: 0x0 LNERR: 0x0
[CPU 0:0:0] NOTICE: SMI Channel 1, SB Mapping 1 -- ERRCNT: 0x1 LNERR: 0x400
[CPU 0:0:0] NOTICE: SMI Channel 0, SB Mapping 0 -- ERRCNT: 0x5 LNERR: 0x100
[CPU 0:0:0] NOTICE: SMI Channel 0, SB Mapping 1 -- ERRCNT: 0x1 LNERR: 0x40
[CPU 0:0:0] NOTICE: SMI Channel 1, SB Mapping 0 -- ERRCNT: 0x0 LNERR: 0x0
[CPU 0:0:0] NOTICE: SMI Channel 1, SB Mapping 1 -- ERRCNT: 0x0 LNERR: 0x0

There does not appear to be any hardware errors recorded under FMA in Solaris or in the ILOM ereports. POST completes fine and the system is bootable.

Symptoms

The system could get non-zero ERRCNT and LNERR values during POST on either SPARC T4-1. SPARC T4-2, or SPARC T4-4 servers.

Cause

Although reported at POST, the origin of the messages is the HC (Host-Config) memory controller (MCU) calibration process. They are not indicative of a memory DIMM, memory controller (MCU) or L-cache issues.

Solution

No hardware should be replaced because of the these non-zero ERRCNT and LNERR values during POST. They are part of the normal start up of the system and nothing to be concerned about.

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