Asset ID: |
1-72-1011054.1 |
Update Date: | 2017-02-02 |
Keywords: | |
Solution Type
Problem Resolution Sure
Solution
1011054.1
:
Sun Fire[TM] v1280, E2900, 3800, 4800, 4810, 6800, E4900, E6900, and Netra 1280, 1290 Server: Missing/Improper Seeprom CPU Speed information.
Related Items |
- Sun Fire 4810 Server
- Sun Fire 3800 Server
- Sun Netra 1290 Server
- Sun Fire 6800 Server
- Sun Fire E6900 Server
- Sun Fire E2900 Server
- Sun Fire V1280 Server
- Sun Fire 4800 Server
- Sun Fire E4900 Server
- Sun Netra 1280 Server
|
Related Categories |
- PLA-Support>Sun Systems>SPARC>Enterprise>SN-SPARC: SF-x8x0/Ex900
- _Old GCS Categories>Sun Microsystems>Servers>Midrange Servers
|
PreviouslyPublishedAs
215220
Applies to:
Sun Fire E2900 Server - Version Not Applicable and later
Sun Fire 4810 Server - Version Not Applicable and later
Sun Fire 6800 Server - Version Not Applicable and later
Sun Netra 1280 Server - Version Not Applicable and later
Sun Netra 1290 Server - Version Not Applicable and later
All Platforms
Symptoms
POST fails the CPU in POST.
setkeyswitch or testboard fails the CPU's
Snapshot of the testboard :
:
:
PostTestSequencer.testListSequencer: Test Large Tag Arrays and Enable MMU
cpuCD All agents under test failed Post
PostTestSequencer.phaseSequencer: Cpu basic tests
cpuCD All agents under test failed Post
PostTestSequencer.sequencer: Memory tests
cpuCD All agents under test failed Post
:
:
{/N0/SB4/P0} Passed
{/N0/SB4/P1} Passed
{/N0/SB4/P2} Failed
{/N0/SB4/P3} Failed
:
:
setkeyswitch on for the domain shows the following error messages :
:
Testing CPU Boards ...
:
Sep 14 23:56:00 e4900a-ssc1 Domain-A.POST: {/N0/SB4/P2} ERROR: Missing/Improper Seeprom CPU Speed information
Sep 14 23:56:00 e4900a-ssc1 Domain-A.POST: {/N0/SB4/P3} ERROR: Missing/Improper Seeprom CPU Speed information
Sep 14 23:56:00 e4900a-ssc1 Domain-A.POST: {/N0/SB4/P2} ERROR: Missing/Improper Seeprom CPU Speed information
Sep 14 23:56:00 e4900a-ssc1 Domain-A.POST: {/N0/SB4/P3} ERROR: Missing/Improper Seeprom CPU Speed information
:
:
{/N0/SB4/P0/C0} Passed
{/N0/SB4/P1/C0} Passed
{/N0/SB4/P0/C1} Passed
{/N0/SB4/P1/C1} Passed
{/N0/SB4/P2/C0} Failed
{/N0/SB4/P3/C0} Failed
{/N0/SB4/P2/C1} Crunched
{/N0/SB4/P3/C1} Crunched
{/N0/SB4/P0} Passed
{/N0/SB4/P1} Passed
{/N0/SB4/P2} Failed
{/N0/SB4/P3} Failed
:
:
seprom contents of sb display CPU C/D's speed as 0MHz.
ssc0:SC[engineering]> sepromupdate sb4 -display
Section at 0x0000 length 0x1800 version 0x0001 numSegs = 6 CRC = 6b
1/6: Segment at 0x0042 name 'ID' length 0x007d (used: 0030) Prot 000041b6
SgCpuSpeed Record at 0x0000 tag = 0xf000280000000000 class E 0.40
CPU A Serial = 00000032438e0927 Speed = 1200MHz
CPU B Serial = 00000032438e0c87 Speed = 1200MHz
CPU C Serial = 0000000000000000 Speed = 0MHz
CPU D Serial = 0000000000000000 Speed = 0MHz
showfru -v -r manr shows :
Component Part # Serial Description Date Time Vend Location
--------- ------ ------ ----------- ---- ---- ---- --------
/N0/SB4 501-6520-05-50 A03308 CPU Board V 04/01 06:10:03 0301 Penang, M3 2004 PST alaysia
The above System Board was working with 1200MHz CPU speed and during a platform power reset the SB CPU's(A/B/C/D) seeprom lost the CPU speed information
Cause
Due to seeprom either missing or having improper CPU speed shows 0MHz for USIV procs.
Solution
Replace the System Board if it fails the POST with the above error messages.
POST is not able to get the actual speed of the CPU from the seeprom contents & hence fails it.
Relief/Workaround
The CPU speed can also be set using the engineering mode command sepromupdate, but its recommended to collaborate for such issues for tracking purpose
and follow the resolution of replacing the System Board or follow the instructions given.
Do ensure that proper situation (i.e. whether the SB was in the domain & domain crashed, there was a power outage or POR was carried out,
SC was hung or was resetting, etc) is mentioned in the collaboration.
Engineering mode on Main SC:
sepromupdate SBx -cpu_speed A 1200
power off SBx
power on SBx
Keywords: seeprom, improper, missing, failed, crunch
Attachments
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